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Freescale ships new mobile multimedia SoCs

Jun 8, 2005 — by Henry Kingman — from the LinuxDevices Archive — views

Freescale will ship two high-end SoCs (system-on-chip processors) for mobile multimedia applications in June. The ARM11-based i.MX31 and i.MX31L clock from 532MHz to 665MHz, but rival faster chips thanks to an advanced crossbar switch, FreeScale says. They include extensive power management, graphics, and security features, and target mobile entertainment devices.

Freescale says the i.MX31 processors are ideal for multi-tasking applications in which 3D graphics, video play-back, and messaging applications must run concurrently. The chips feature leading power management, security management, and image processing technology, the company says.

i.MX31/L

The i.MX31 and i.MX31L are based on an ARM 1136JF-S core, the same core used in the MXC “mobile phone on a chip” that began sampling last week. Freescale's previous top-of-the-line mobile multimedia processor, the i.MX21, used an ARM9 core.

The chips feature 128 KB of L2 unified cache, and include a 6×5 “Smart Speed” crossbar switch that “nearly eliminates wait states,” Freescale says, allowing them to “take advantage of parallelism to operate at the equivalent performance of a 3GHz processor, yet minimize power consumption.”

FreeScale says it created an “effective cycles per instruction” (eCPI) benchmark to show off the capabilities of the i.MX31 and i.MX31L. The company did not reveal specific eCPI figures for the chips, but says their eCPI ratios are very low.

Both chips offer advanced power management features, including DVFS (dynamic voltage and frequency scaling) and DPTC (dynamic process temperature compensation). Power usage can be further reduced with the addition of one of FreeScale's PMUIs (power management and user interface) chips, FreeScale says.

Both chips have on-chip display/TV controllers and IPUs (image processing units) that FreeScale claims can deliver video at 30fps while minimizing CPU involvement. The i.MX31 adds 2D/3D graphics acceleration supporting OpenGL, and a VPU (vector floating point unit). Both chips include an integrated Jazelle Java accelerator.

Both chips utilize Freescale's Independent Platform Security Architecture, a combination of hardware and software security features said to provide a high level of confidence for carriers, content providers, and consumers.

The i.MX31 and i.MX31L also feature advanced USB capabilities, which can be used to interface with PCs, PC peripherals, WiFi and Bluetooth radios, or cellular baseband chips, FreeScale says.


i.MX31 block diagram

Peripheral interfaces include an external memory bus supporting 133MHz DRAM, 266MHz Mobile DDR, 8/16-bit NAND Flash, and PSRAM; CMOS/CCD camera sensor interface; dual USB on-the-go (OTG) host support, dual MMC/SD and Memory Stick Pro interfaces; PCMCIA and CompactFlash interfaces, an ATA-6 hard drive interface, an audio MUX; an IrDA/fast IrDA/keypad interface; five UARTs; dual SSI/I2S; and dual configurable SPI (serial peripheral interface).

Freescale says its i.MX family supports embedded Linux, Windows CE, Palm OS, and Symbian OS.

Freescale's senior VP of Wireless and Mobile Systems, Frankz Fink, said, “Our i.MX31 processors provide a high octane multimedia engine with exceptional power management techniques.”

Availability

The i.MX31 and i.MX31L processors are expected to begin shipping to select customers by the end of June 2005, built on 90nm CMOS process technology and packaged in a 457 ball, 0.5 mm pitch MAPBGA.


 
This article was originally published on LinuxDevices.com and has been donated to the open source community by QuinStreet Inc. Please visit LinuxToday.com for up-to-date news and articles about Linux and open source.



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