STMicroelectronics (STM) is sampling an inexpensive ARM-based SoC (system-on-chip) with a 200K-gate configurable logic block. The SPEAr Head (structured processor enhanced architecture) integrates USB 2.0 host/device and 10/100 Ethernet interfaces, and targets embedded control applications such as digital engines for printers and scanners. It runs Linux, among several other embedded OSes.

The SPEAr Head is based on an ARM926EJ-S core clocked at 266MHz. The core includes 32KB of instruction and 16KB of data cache, along with 8KB each of data and instruction TCM (tightly coupled memory).

The SPEAr Head additionally integrates 200K gates (ASIC equivalent) of configurable logic, connected to four 4KB banks of SRAM. Developers can design custom logic using an ASIC-like approach, or else develop with an external FPGA before mapping the finalized code onto the configurable logic device, STM says.

SPEAr Head architecture diagram
On-chip peripheral interfaces include:

• 2 x USB 2.0 host ports
• 1 x USB 2.0 device port supporting high-speed mode
• Ethernet 10/100 MAC
• 16-channel 8-bit A/D converter
• I2C interface
• 3 x UARTs
• SDRAM memory interfaces at 133MHz supporting DDR and SDR
• SPI interface supporting serial FLASH/ROM
• 1 x USB-dedicated PLL
• 1 x dithered system PLL
• RTC (real-time clock)
• Watchdog
• 4 x general purpose timers
• Target OSes — Linux, Nucleus, ultron, and VxWorks

Vittorio Peduto, GM of computer systems, said, “Specific IP, such as a dithered PLL, special I/Os to minimize on-board reflections, automatically reconfigurable DDR/SDRAM interface, and a distributed DMA architecture make this chip unique in the market.”

Availability

The SPEAr Head is currently sampling, with development boards expected in December. Volume pricing is expected to be about $12.

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