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Synthesizable core runs uClinux on new RISC architecture

May 19, 2005 — by Henry Kingman — from the LinuxDevices Archive — views

Cambridge Consulting has unveiled a new 32-bit synthesizable processor core with a new RISC instruction set that will run uClinux. The company says the XAP3 core was optimized from the beginning for low system cost, low power consumption, and high code density, without sacrificing performance.

The XAP3 core targets FPGAs (field-programmable gate arrays), ASICs (application-specific integrated circuits), ASSPs (application-specific standard products), and SoCs (system-on-chips). It supports Cambridge Consulting's own ANSI-C compiler, as well as GCC C/C++ compilers.

Cambridge Consultants says it has successfully compiled uClinux for the XAP3 architecture using GCC, and it plans to release a uClinux port for XAP3 later this year. A specific date has not been announced, however.


XAP3 architecture
(Click to enlarge)

Cambridge Consulting lists key features of XAP3 as follows:

  • Load-store RISC architecture
  • Very high code density
  • Von Neumann machine
  • Flexible data access
  • Programmer-friendly architecture

Further details can be found on Cambridge Consulting's website.


 
This article was originally published on LinuxDevices.com and has been donated to the open source community by QuinStreet Inc. Please visit LinuxToday.com for up-to-date news and articles about Linux and open source.



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