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Broadcom ramps up second-generation multi-core MIPS64 SoCs

Oct 6, 2004 — by LinuxDevices Staff — from the LinuxDevices Archive

Broadcom expects to sample two dual-core SoCs (system-on-chips) in Q4, 2004, and two quad-core SoCs in Q1, 2005. Like Broadcom's existing dual-core SiByte BCM1250, the new multi-core SoCs will use MIPS64-based SB-1 cores, and will target data networking and communications, security, storage, 3G wireless infrastructure, and high-density computing applications.

Why multi-core?

A variety of chip vendors have recently announced multi-core SoC designs, including PMC-Sierra (MIPS), Freescale (PPC), Cavium (MIPS), and ARM (ARM). Multi-core advantages include a better ratio of performance to power usage, less heat dissipation, and a smaller physical footprint. One prime market for multi-core SoCs appears to be networking equipment such as firewalls that deeply inspect packets or perform compute-intensive spam filtering.

Broadcom claims the most powerful of its new multi-core SoCs will deliver up to 10,000 Dhrystone MIPS (million instructions per second), 32 billion floating-point operations per second (GFLOPS), 20 million packets per second of L3 forwarding performance, 100 Gigabit per second (Gbps) memory bandwidth, and up to 145 Gbps I/O bandwidth, while drawing under 25 Watts.

Second-generation design

Broadcom says its new multi-core chips build on the success of the original SiByte chip, the dual-core BCM1250, which it says pioneered the HyperTransport interconnect and was “the embedded processor industry's first dual-core SoC.” HyperTransport is a high-speed inter-chip bus that Broadcom says can connect cores in discrete chips as if they were on the same die. The BCM1250 gained Linux support in September of 2002.

Broadcom says the BCM1250 helped it achieve the largest market share gain among vendors of communication and network processors, as measured by IDC. IDC's program manager Sean Lavey said, “Over the past two years, Broadcom has achieved significant growth from its SB-1-based MIPS processors, especially within certain key communication infrastructure OEMs. This extension of its product line will take Broadcom's multi-core architecture to an even higher level of performance.”

Tom Halfhill, a senior analyst with In-Stat/MDR, said, “Broadcom's new processors build on the experience and success the company has gained with its dual-core BCM1250 processor. [They] leverage the proven SB-1 MIPS-compatible processor core optimized for networking and communications. They're also software compatible with the BCM1250 and the single-core BCM112x.”

Meet the new chips

Like the older BCM1250 and single-core BCM112x, the new SiByte chips are based on Broadcom's SB-1 core. Broadcom describes the core as “a custom quad-issue in-order implementation of the MIPS64 architecture, with 32KB of instruction cache, 32KB of data cache, and hardware support for cache coherency. The SB-1 has two load-store pipes, two integer execute pipes, two floating-point execute pipes, and includes support for the MIPS-3D ASE and '.ob' format MDMX ASE instructions.”

In addition to two or four SB-1 cores, the new SiByte chips integrate:

  • A multichannel 400 MHz double data rate 2 (DDR2) memory controller supporting DDR-400 and DDR2-800, for a claimed peak bandwidth of 100 Gbps. The controller can be configured for two 64-bit wide channels or four 32-bit wide channels, and supports up to 16GB of memory with 1GB DRAM technology
  • Four Gigabit Ethernet interfaces
  • A single 64-bit PCI-X interface running up to 133 MHz
  • Up to three independently configurable 19.2 Gbps full duplex channels interconnected by a 256-bit wide high-speed internal bus and connected to the processor cores via an on-chip, 256 Gbps cut-through switch. Each port can be configured by the customer to operate in SPI (Standard Packet Interface) 4.2 or 16-bit HyperTransport (HT) mode, running up to 600 MHz DDR.

Additionally, the new SiByte chips support symmetric multiprocessing (SMP), said to avail all cores of the same shared pool of system resources, including memory and I/O. They also support ccNUMA (cache-coherent non-uniform memory access), which enables up to eight SiByte chips — or up to 32 SB-1 CPU cores — to communicate over HyperTransport as if they were all cores on a single chip, a feature said to be useful in dense computing and cluster applications such as this example.

The new SiByte SoCs will be manufactured using 90nm CMOS process technology, Broadcom says.

The new SiByte chips include: (click chip names for block diagrams)

BCM1255 BCM1280 BCM1455 BCM1480
# of CPUs 2 2 4 4
L2 Cache 512KB 1MB 1MB 1MB
DDR2 Support Yes Yes Yes Yes
PCI-X 1 x 64-bit 1 x 64-bit 1 x 64-bit 1 x 64-bit
# of SPI-4/HT Ports 0 3 0 3


The BCM1255 and BCM1280 are expected to sample in the fourth quarter of 2004. The BCM1455 and BCM1480 are expected to sample in the first quarter of 2005. Evaluation board platforms are expected before 2005.

Pricing for direct OEM customers for 10,000 piece quantities at 1 GHz starts from $599 each for the dual-core BCM12xx products and $999 each for the quad-core BCM14xx products.

Previous multi-core Broadcom chips enjoyed commercial support from MontaVista and BSD support from Wasabi, although neither has yet made any announcements concerning the second-generation SiByte chips.

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