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Multi-core PowerPC chips target telecom apps

Jun 25, 2007 — by LinuxDevices Staff — from the LinuxDevices Archive — 1 views

Freescale has announced a new family of multi-core, PowerPC-based communications processors built on 45nm process technology. Three software development tools vendors have already pledged to support the Multicore Communications Platform (MCP) chips, which are expected to sample late in 2008.

90nm vs. 45nm
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Freescale says its 45nm geometry will enable a 50 percent reduction in die size and power, compared to the 90nm geometries it currently uses. The MCP chips will integrate multiple Freescale's e500-mc cores clocked at a target frequency of 1.5GHz. Each core will have its own L2 cache, along with “multiple megabytes” of shared L3 cache.

MCP architecture diagram
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The cores will connect via a new “CoreNet” fabric supporting up to 32 cores. The fabric is said to “eliminate bus contention, bottlenecks, and latency issues,” compared to multi-core chips with a shared bus/shared memory architecture. Support for “heterogeneous core implementations” is another touted CoreNet feature — possibly referring to support for Freescale's programmable QUICC processing elements.

Other touted MCP chip features include:

  • “Leverages” an unspecified hypervisor environment
  • Lots of hardware acceleration IP available:
    • Pattern matching
    • Decompression/Compression
    • Crypto security
    • Table lookups for packet parsing and flow classification
    • “Data path resource management”

Multi-core development tools support

Freescale has promised to endow the MCP chips with hooks aimed at providing visibility into the complex interactions associated with multicore development. These include “integrated instruction trace, watchpoint triggers, cross event triggers, performance monitoring, and other debug features as defined by the Power ISA.”

Freescale said it will work closely with multiple tools vendors to ensure MCP chip support concurrent or in advance of sample availability. Tool vendors pledging to support the Freescale's MCP chips include:

  • Wind River, for its embedded Linux and VxWorks platforms and tools
  • MontaVista, for its “Linux Professional Edition” embedded Linux platform and tools
  • Virtutech, for “cycle-accurate” models of select MCP chips this year

Virtutech's Simics simulation tool, in particular, is touted by Freescale as a product likely to become integral to MCP developer workflows, as illustrated below.

MCP development using Simics
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Freescale expects to sample the first MCP-family chips toward the end of 2008. MontaVista and Wind River have both said they plan to provide Linux support for the chips concurrent with the processors' availability. Virtutech says its Simics “whole system” emulation tool will be available with MCP chip models prior to the end of the year, giving a headstart to telecommunications equipment manufacturers (TEMs) and customers of Freescale's MCP chips.

Meanwhile, Virtutech, MontaVista, and Wind River each tout their products' support for Freescale's first multi-core PowerPC chip, the MPC8641D, which is currently sampling.

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