FPGA (field programmable gate array) vendor Altera is shipping a new version of its FGPA design tool that runs on Linux hosts. Quartus II 6.0 includes new features aimed at high-density designs, including today's 90-nm designs as well as forthcoming 65-nm designs, the company says.

Altera lists the following new features in Quartus II 6.0:

• TimeQuest timing analyzer natively supports SDC (Synopsys Design Constraints), described as an “industry-standard” format
• A project manager interface with per-block timing constraint management, for collaborative, high-density design development
• Faster RTL (register transfer level) implementation through support for design constructs of IEEE 1800-2005 Standard SystemVerilog syntax hardware description and verification language
• Enhanced I/O pin planner, for easier integration of Altera's intellectual property, and simpler pin assignments
• Expanded board-level design support, such as HSPICE models of Stratix(R) II single-ended outputs

Lonn Fiance, director of Strategic Alliances at Synopsys, stated, “FPGA designers will be able to achieve timing closure more quickly by directly reading the industry-standard SDC timing constraint format into TimeQuest timing analyzer. Adoption of the SDC format will increase productivity among FPGA designers and further advance the deployment of a standard timing verification methodology across the semiconductor industry.”

Availability

Subscription editions of Quartus II 6.0 are available now, with free upgrades to current subscribers. Subscriptions include ModelSim Altera edition, and licenses to Altera's “IP Base Suite.” It supports RHEL (Red Hat Enterprise Linux) 3.0 and 4.0, as well as Solaris and Windows.

 
This article was originally published on LinuxDevices.com and has been donated to the open source community by QuinStreet Inc. Please visit LinuxToday.com for up-to-date news and articles about Linux and open source.