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Intel reveals Silverthorne details

Feb 4, 2008 — by LinuxDevices Staff — from the LinuxDevices Archive — views

Intel will reveal technical details about its forthcoming Silverthorne SoCs for mobile devices at a chip conference this week. Based on a new micro-architecture with an in-order instruction pipeline, and built on 45 nanometer technology, the x86-compatible chips will use a tenth the power of Core2 “ULV” chips, Intel says.

At the IEEE's International Solid State Circuits Conference, Intel plans to present more than a dozen technical papers that will range from a first look at its new quad-core Itanium processor to developments in new memory technology to an update on Intel's tera-scale processor. However, the chipmaker will focus most of its attention on Silverthorne, which has been designed for what Intel executives call mobile Internet devices or MIDs. Since the 2007 Intel Developer Forum, company officials have been talking about the new 45-nanometer processor, but the ISSCC conference marks the first time the company's engineers will talk about Silverthorne's technical properties.

Meanwhile, eWEEK's Scott Ferguson has put together an overview of what to expect, based on pre-event interviews with Intel CTO Justin Rattner and microprocessor industry analyst John Spooner. eWEEK coverage can be found here.

Intel unveiled Silverthorne at its Bejing Developer's Forum last April. Silverthorne is slated for use in two-chip “Menlow” chipsets that will support high-density solid-state disks. Although hotly anticipated by mobile developers like those working on Mobile Ubuntu, the new Intel mobile chips were recently criticized by Glenn Henry, president of competitor Via's CenTaur processor division. Henry said Intel “constrained performance and compatibility,” in order to avoid cannibalizing lucrative Core2 mobile sales.

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