IBM has released an evaluation kit for hardware and software engineers interested in evaluating the PowerPC 405 architecture and CoreConnect bus. The PowerPC 405 Evaluation Kit (PEK) includes transaction-level models, along with a variety of tools, specifications, documentation, and evaluation licenses.

IBM says the PEK can be used by software engineers interested in developing boot firmware, operating systems, or application code for the PowerPC 405 architecture, as well as hardware engineers considering the architecture as the basis for custom SoC (system-on-chip) designs.

The PEK includes:

• IBM SystemC transaction-level models for PowerPC 405 and CoreConnect intellectual property (IP) cores
  
• A 60-day downloadable evaluation license of the IBM ChipBench SLD, allowing early architectural and performance analysis
  
• IBM RISCWatch debugger tool
  
• Pre-integrated SoC platform examples for architecture exploration and extensions
  
• Sample application code with tutorial
  
• Enabled-for-GNU-project C compiler (GCC) tool chain
  
• Reference SW API documentation
  
• Reference technical manual and functional specification documents, including:
  • PPC405Fx Embedded Processor Core Specification
  • Universal Interrupt Controller Specification
  • DDR2MC1632B2PLB4 Functional Specification
  • Universal Asynchronous Receiver/Transmitter 16750 Specification
  • 128 Bit Processor Local Bus Architecture Specification
  • 64/32-Bit On-Chip Peripheral Bus Architecture Specification
  • 32-Bit Device Control Register Architecture Specification
  • 32-Bit On-Chip Peripheral Bus Arbiter Specification

About the 405 architecture

IBM says the PowerPC 405 implements 32-bit Power Architecture technology, with extensions for embedded applications, such as:

• A simplified memory management mechanism with enhancements for embedded applications
• An enhanced, dual-level interrupt structure
• An architected DCR address space for integrated peripheral control
• The addition of several instructions to support these modified and extended resources

The 405 core is said to offer high performance and low power consumption while executing at sustained speeds “approaching one cycle per instruction, including loads and stores. It can clock up to 600MHz, and delivers 1.52 DMIPS/MHz, IBM claims. Power usage is listed as 0.2mW/MHz, and the core occupies 2 sq.mm with 16KB/16KB caches, the company says.

The PEK can be downloaded here. Introductory-level details about using the PEK to create SoCs are described here.

 
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