64-bit RISC system-on-chip targets “digital information devices”
Apr 21, 2003 — by LinuxDevices Staff — from the LinuxDevices Archive — 1 viewsToshiba America Electronic Components Inc. announced a new 64-bit RISC system-on-chip processor targeting “digital information device” applications. The device runs at up to 300 MHz clock rates and includes a pair of 10/100 Base-T Ethernet MACs, a NAND Flash memory interface, a dual UART, and more, the company said.
On-chip functions of the TMPR4938XBG-300 system-on-chip processor are said to include . . .
- 300 MHz 64-bit TX49/H3 core, derived from the MIPS RISC architecture
- Memory controller for SDRAM, SRAM, ROM, NOR-Flash
- PCI bus controller
- 8-channel DMA controller
- 3-channel 32-bit timer
- 6-channel interrupt controller
- NAND Flash Memory interface
- Dual 10/100 Base-T Ethernet MAC
- Dual UART
- AC-Link (AC97 Interface)
Support for using the device in embedded Linux based systems will be available from MontaVista software, Toshiba said.
Samples are expected in May 2003, with production quantities mid-2003. OEM pricing will be around $35.
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