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FPGA vendor rev’s design suite

Mar 24, 2008 — by LinuxDevices Staff — from the LinuxDevices Archive — views

[Updated Mar. 25] — Xilinx has upgraded its design suite for field-programmable gate arrays (FPGAs). Intended to the span logic, DSP microcode, and embedded software development phases of FPGA design, the ISE Design Suite 10.1 yields faster runtimes thanks to improved encryption, and also adds support for distributed “implementation runs,” the company said.

In the past, Xilinx has released new versions of its logic tools first, and then followed with the other tools, explained Lisa Washington, the company's marketing and communications expert. “ISE 10.1 Design Suite 10.1 is the first time we have a synchronized the release of all SW tools,” she said.

ISE Design Studio aims to provide a single set of tools spanning the complete FPGA development cycle, including FPGA logic, embedded software, and DSP (digital signal processor) microcode. The suite comprises:

  • ISE Foundation
  • Embedded Development Kit (EDK) with Platform Studio (XPS)
  • System Generator for DSP
  • AccelDSP synthesis tool
  • ChipScope Pro analyzer and ChipScope Pro Serial I/O toolkit
  • PlanAhead design and analysis tool and ISE simulator.

According to Xilinx, ISE Design Suite 10.1 achieves faster runtimes in large part due to its IEEE IP encrypted runtime models, which are based on technology from a joint collaboration with EDA provider Mentor Graphics. Further runtime performance improvements are said to derive from optimized BRAM, DSP, and FIFO simulation models.

Another touted feature is the ability to distribute “implementation runs” across multiple Linux machines. The feature is said to increase productivity for developers using Linux development hosts. Washington explained that an implementation run “is where we take the design net list from synthesis and run place-and-route (PAR) to implement the design for the target FPGA.”

Additional features and capabilities include:

  • The PlanAhead Lite tool provides a subset of the Xilinx's full PlanAhead floorplanning and analysis capabilities tool. Its “PinAhead” technology is said to simplify the complexities of managing the interface between the target FPGA and PCB by providing early pinout definitions using design rule checks. This minimizes pinout-related changes downstream, says Xilinx.
  • An upgraded power analysis tool is said to improve power estimation, offering tools to analyze power by blocks, hierarchy, power rails, and resources used. By taking advantage of improvements in the map and the place & route algorithms, claims Xilinx, users can reduce dynamic power in their designs by an average of 10-12 percent.

Xilinx provided testimonials from beta users, and although their figures did not match its own claimed doubling of run times and 38 percent faster performance, the customers appeared to be impressed.

Stated Yasuhiro Ooba, senior engineer in the Photonic Systems Group at Fujitsu, “The ISE Design Suite 10.1 has [provided] up to 80 percent run time improvement. Faster run times provide tremendous savings in development time.”

Stated Honda Yang, logic designer at I/O virtualization vendor Xsigo Systems, “Using SmartXplorer, we achieved 20 percent faster performance.”

In November, Xilinx added the option of a memory management unit (MMU) to the royalty-free 32-bit soft-core MicroBlaze v7 processor it offers for its low-end “Spartan” and high-end “Virtex” FPGAs. This permitted MicroBlaze to run complex OSes such as Linux, including LynuxWorks's commercially supported BlueCat-ME (MicroBlaze Edition) distribution. Then in January, the company bundled the MicroBlaze kit with free 10/100 Ethernet, serial UART, I2C, and FPU (floating point unit) IP cores. In February, Xilinx released a Linux-based development kit for MicroBlaze-based Spartan FPGAs used in low-cost Ethernet-based designs.


The ISE Design Suite 10.1 is available now, says Xilinx, at prices ranging from $500 to $2500. More information, plus a free 60-day evaluation version can be downloaded here.

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