Cavium Networks is sampling multi-core network processors targeting mid- to high-end networking and storage devices based on Linux. The Octeon EXP family includes models with four to 16 cores that can integrate both data- and control-plane processing on a single processor, the company claims. The chips target routers, intelligent switches, multi-service access equipment, storage servers, multi-protocol storage switches, border session gateways, and wireless infrastructure equipment.

Data- and control-plane convergence

Cavium says all networking equipment has both control and data planes. A router's control plane typically routes traffic on an application processor, while its data plane processes packets on a communications processor or ASIC (application-specific integrated circuit), for example.

At low bandwidths, both data- and control-plane processing can be handled by a single-core chipset. As performance requirements increase beyond several hundred Mbps, control and data functions today are typically split between separate processors — or separate control- and line-cards in larger chassis-based equipment.

Cavium says integrating control- and data-plane processing into a single multi-core chipset halves BOM (bill-of-materials) costs and power and space requirements, while speeding inter-processor communication. Better performance allows tighter data- and control-plane integration, the company explains, better supporting the richer data-plane functionality required to support quality-of-service (QoS), video-over-IP, and other emerging network requirements and applications.

An important added advantage of integrated control- and data-plane processing is the ability to scale the same software from multi-100Mbps devices to devices supporting multi-gigabit rates, the company says. Additionally, unlike networking equipment utilizing DSP coprocessors or ASICs, the Octeon EXP chips offer a standard C/C++ software programming model.

Flexible deployment model

Separate OSes can be run on each core, or a single symmetrical multiprocessing OS can be run across all cores. Alternatively, a multiprocessing OS such as Linux can handle both control- and data-plane processing, with processor affinity (asymmetric multiprocessing) ensuring adequate real-time performance. The chip can also support simple run-to-completion or pipelined data-plane software running on bare metal, to preserve software investments for carrier equipment providers and network operators, Cavium says.

The company says that “the vast majority” of its customers use Linux in new designs. Many use Linux only in the control plane, while others also use Linux in the data plane, with the code running in “processor affinity” mode. The Octeon's flexible deployment model allows companies to take an incremental approach toward transitioning to Linux, the company says.

The Octeon EXP 38xx series chips

Cavium is a MIPS64 rel. 2 ISA (instruction-set architecture) licensee, and the first company to achieve MIPS64 rel. 2 silicon, it claims. Octeon cores are based on the standard MIPS64 rel. 2 instruction set, along with “undocumented” packet acceleration instructions, the company says.

Octeon EXP block diagram
(Click to enlarge)

The Octeon EXP chips are available with four to 16 cores, clocked at 600MHz. Each core has 32KB of instruction cache, and 8KB of data cache, along with a 2KB write-back buffer. A coherent bus provides support to a shared L2 cache of 1MB, along with access to a high-performance memory controller supporting up to 16GB of 144-bit wide ECC-protected DDR II DRAM at claimed data rates up to 800Mbps.

The Octeon EXP chips feature integrated network controllers and MACs. Two packet interfaces can support four gigabit Ethernet interfaces each, or two “SPI-4.2” (system packet interface) interfaces, each of which supports throughputs up to 10Gbps.

The Octeon EXP includes hardware support for what the company likens to “packet DMA” — a dedicated TCP/IP unit, compression/decompression engine, packet scheduler, and 16 regex engines handle layer 2-4 parsing, error checking, tagging, and memory allocation. The packet scheduler sends an available core a tag noting its position in memory, saving processor cycles. After processing, the packet is sent to a dedicated packet output processor, which routes it to the appropriate interface without requiring additional processor cycles.

Dual hyper-access low-latency memory controllers support up to 1GB of 18-bit-wide low-latency RLDRAM2 / FCRAM2 dedicated to packet input pre-processing. This memory can also be used to connect one or more TeleCommunications Access Methods (TCAMs) for offloading lookups to an external hardware device, Cavium says.

Other I/O includes a 64-bit, 133MHz PCI-X interface, GPIO, two serial ports, and a boot-Flash ROM interface.

Cavium says the Octeon EXP chips offer up to 9.6GHz of processing speed, and 19.2 billions of instructions per second. Application performances between 2Gbps and 10Gbps require between 10 Watts and 25 Watts of power, the company claims.

Linley Group analyst Linley Gwennap said, “As OEMs are adding voice and video functions to both enterprise and infrastructure equipment, the greater routing, provisioning, and quality-of-service requirements are driving a convergence of control and data plane processing. Octeon's multiple general-purpose processors and extensive data-plane acceleration support this convergence at multi-gigabit speeds, while improving time to market with a simple programming model.”

About Cavium

Cavium is a privately held fabless semiconductor design house headquartered in Mountain View, Calif. It employs around 115 people, including what remains of DEC's Marlboro, Mass. Alpha processor design team, it says. It also has a design center in Hyderabad, India.

Cavium says the market for processors used in data- and control-plan processing amounts to more than a billion dollars in annual sales. The company has received $60M in venture funding, and expects to reach profitability this year.

Availability

The Octeon EXP CN38xx line is currently sampling in 4-, 8, 12-, and 16-core models, along with a developer kit, simulator, and Linux toolchain and reference applications. Pricing will range from $350 to $650, in 10K unit quantities. The chips are built by PSMC on a 0.13-micron process with excellent yield and no production capacity issues, the company says, adding that a move to 90-nm process technology is planned.

Cavium began sampling two- and four-processor CN34xx-series Octeon chips in Q1 of this year.

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