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Nanos get higher speed, expanded instruction set

Nov 3, 2009 — by LinuxDevices Staff — from the LinuxDevices Archive — 2 views

Via Technologies has introduced new versions of its 64-bit Nano processors. The Nano 3000 series, available in speeds from 1.0 to 2.0GHz, offers up to 20 percent higher performance, and adds support for Intel's SSE4 (streaming SIMD extensions 4) instruction set, says Via.

Via's six newly-announced Nano 3000 processors are available in an L-series ("low-power") for mainstream desktop and mobile PC systems, and in a U-series ("ultra-low-power") for mini-notebooks and small form factor devices. They use the same 21mm x 21mm nanoBGA2 package as the original Nano, and once again are being manufactured — likely by Fujitsu — using a 65nm process.

According to Via, the Nano 3000 devices are pin-compatible with earlier Nanos (see later in this story for background) and the earlier C7 and Eden CPUs, and still feature only single cores. However, in addition to a clock speed bump to 2.0GHz at the high end, the revised Nanos are said to add support for Intel's SSE4 instruction set extensions, plus Via's VT virtualization technology. (Previous Nanos supported only SSE3, just like Intel's own Atom.) 

As a result, says Via, the Nano 3000 series can deliver up to 20 percent greater performance than previous Nanos, while using up to 20 percent less power. The chipmaker released the graphics below, suggesting that when clocked at 1.6GHz, the Nano 3000 outperforms Intel's Atom N270 by up to 45 percent on the PCMark 05 v120 benchmark, and 51 percent on the 3DMark2006 benchmark. (Of course, Nano CPUs are designed to use Via's integrated northbridge/southbridge chips such as the VX855, known to outpace the integrated graphics provided by Intel's 945GSE chipset.)

Nano 3000 benchmark results
Source: Via Technologies

Ironically, Via didn't announce a Nano 3000 part designed to run exactly at 1.6GHz. Instead, as the table below shows, the new CPUs (highlighted in red) range from the 1.0GHz U3500 to the 2.0GHz L3100. All feature 1MB second-level caches and 800MHz frontside bus frequencies, as did the earlier Nanos.

Name Speed Idle power Maximum power
(TDP max)
L3100 2.0GHz 500mW n/s
L3050 1.8GHz 500mW n/s
U3200 1.4GHz 100mW n/s
U3100 1.3+GHz 100mW n/s
U3300 1.2GHz 100mW n/s
U3500 1.0GHz 100mW n/s
L2100 1.8GHz 500mW 25.5W
L2200 1.6GHz 100mW 17W
U2400 1.3GHz 100mW 8W
U2500 1.2GHz 100mW 6.8W
U2300 1.0GHz 100mW 5W

Via's Nano 3000 series (in red) compared to earlier Nanos

While claiming both "flawless playback of high bit-rate 1080p HD video" and lower power consumption for the new Nano 3000 chips, Via didn't back up the latter by making TDPs public. Idle power consumption, meanwhile, appears to be on par with previous Nanos, as our table shows.

A continuing point of pride for Via is its PadLock security engine, once again featured on the Nano 3000 CPUs. Offered at least since the 2003 introduction of the Eden-N, PadLock offers hardware-based Advanced Encryption Standard (AES) functionality, and imposes significantly less overhead than software-based encryption, according to the company.


Via's Esther (used in the C7 and Eden) and Isaiah (used in the Nano) microarchitectures were designed by the company's CenTaur chip unit, headed up by Glenn Henry, a former IBM engineering fellow. Whereas Esther — like Intel's Atom — uses in-order execution, for the lowest power and size requirements, Isaiah uses out-of-order execution, similar to Intel's Core Duo architecture. Isaiah added compatibility with the 64-bit architectures already used by Intel and AMD, plus SSE3 media processing instructions. Another touted Isaiah feature was a reworked floating point unit.

A block diagram of the Via Nano

The Nano processors were the first 64-bit, superscalar, speculative out-of-order processors in Via's x86 platform portfolio, according to the company. They can decode three full x86 instructions per clock, generate three fused (internal machine instructions) micro-ops per clock, issue (speculatively and out-of-order) seven execution micro-ops per clock to seven execution ports, and retire three fused microops per clock.

A conceptual diagram of Via's Nano 3000 architecture

As the above conceptual picture illustrates, the Nano processors include pipelines that fetch x86 instruction bytes and translate them into micro-ops. The x86 instructions and micro-ops proceed in program order down the top left ("in-order") portion of the pipeline. The "speculative" label refers to the fact that the processor may not be actually fetching the correct program instructions (in cases of a branch misprediction, for example). "Out-of-order" issue and execution happens when the pipeline components take the translated micro-ops and issue them to the appropriate execution units. This happens whenever inputs are available, not necessarily in program order.

According to Via, the Nano's L2 cache is designed to support a wide variety of sizes with minimal implementation effort. In addition, the L2 cache is "exclusive," meaning that L1 cache contents do not reside in it. This effectively increases L2 cache size compared to "competitor architectures" with inclusive caches, Via says. At the same time, the architecture was designed for multi-core, multiprocessing friendliness, Via says.

Touting the Nano's "significant emphasis on high-performance floating-point execution," Via says the processor can execute four floating-point adds and four floating-point multiplies every clock. A "completely new algorithm for floating-point results in the lowest floating-point add latency of any x86 processor," the company said in a 2008 whitepaper about the Isaiah architecture. In addition, the integer data path for SIMD integer (SSEx) instructions is 128-bits wide, and almost all SSEx instructions (including all shuffles) execute in only one clock.


According to Via, its Nano 3000 CPUs are sampling now for OEMs and motherboard vendors, and will enter mass production during the first quarter of 2010. More information may be found on the company's website, here.

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