San Jose, CA — (press release excerpt) — Lexra announces today the industry's highest performance processor based on the MIPS32 architecture for use in its SOCs for High-Touch packet processing applications.

The 500 MHz LX4580 implements Hardware Multi-Threading (HMT) in order to minimize idle time due to cache misses, achieving a 3x performance improvement compared to other 32-bit CPUs in High-Touch applications. The LX4580 processor represents the achievement of an important milestone in the development of Lexra's new family of network communications ICs to be introduced later this year.

In today's Internet economy, High-Touch packet processing applications thrive in security, storage infrastructure, and Internet appliances in an enterprise network. The aggregation of services at the edge of the public network is another hot spot for such applications. High-Touch applications are characterized by the need to maximize the overall throughput for streaming data while running code developed in high-level languages such as C or C++. The code applies dynamic and sophisticated policies to the data streams, requiring deep packet inspection.

Data caches are simply not big enough for stateful, sophisticated processing in High-Touch applications when data rates exceed OC-3 speeds. The large data set with low locality of reference results in high data cache miss rates and low (less than 30%) effective utilization of a single-threaded processor. The traditional approach has been to use the fastest affordable PC-class CPU.

The LX4580 incorporates Lexra's innovative, fine-grained Hardware Multi-Threading (HMT) technology with support for a fully cache-coherent memory model. It implements the MIPS32 architecture, including recent architectural enhancements, along with Lexra proprietary instructions for optimized packet processing. It supports 64KB of instruction cache and 16KB of data cache, each with 4-way set associativity and parity protection. The LX4580 achieves 500MHz frequency worst case in typical 0.13um processes. The database is fully synthesizable and can be easily ported between process technologies.

Lexra has implemented HMT using the licensee-dependent capabilities provided by the MIPS32 architecture. Instructions are issued round robin to four alternate pipeline flows, each with an independent program counter and general register file. The four pipeline flows support four independent execution threads. In the event of a thread's cache miss, that specific thread is not issued again until its cache miss is fully serviced. As few as two active threads can maintain 100% CPU utilization. The load-to-use delay is typically zero cycles, even with the LX4580's 7-stage pipeline. Lexra's novel instruction issue rules simplify the CPU design, thereby enabling a higher processor frequency for a given process technology without aggressive design techniques. In addition, stall cycles resulting from jumps, mis-predicted branches and load interlocks are also completely eliminated.

For typical High-Touch programs, the LX4580 delivers 3x performance benefits relative to a similar single-issue CPU. Support for a fully cache-coherent memory model and core footprint of only 3.8mm(2) in 0.13um technology enables on-chip multiprocessor product implementations that can easily scale over a wide range of performance and cost.

Lexra is partnering with leading third-party software companies to develop operating systems and tools for easy design-in of its SOC products based on the LX4580. The LX4580 supports Linux with full SMP support running on all four hardware threads. High-Touch applications exploit the advanced scheduling of Linux SMP to achieve the general-purpose programmability needed. Alternatively, VxWorks is supported on one thread, with the other threads functioning like coprocessors.

The LX4580 CPU core is the foundation for multiple SOC network communications ICs from Lexra. The first Lexra product based on LX4580 will be announced in Q4, 2002.

 
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