Half Moon Bay, CA — (press release excerpt) — OnCore Systems Corporation today began shipping comprehensive support for IBM's PowerPC 405 embedded processor, Revision D, the latest release of this high-power embedded processor line. IBM's integrated, cost-conscious “system-on-a-chip” PowerPC 405 RISC processors deliver up to 375 MIPS of processing power and come equipped with an integrated MMU plus a… broad range of embedded peripherals, including on-chip Ethernet, a code decompression engine, a PCI bus interface, on-chip SRAM, and intelligent multifunction I/O interfaces.

The 405's MMU has been optimized for use with embedded designs. An integral element of this design is the Translation Lookaside Buffer (TLB). For many
PowerPC processors, TLB translations are processed using fixed, hardware-enabled algorithms. In contrast, IBM enabled embedded designers to optimize TLB translations for the PowerPC 405 by allowing these functions to
be controlled by software. The OnCore development environment taps the full power of 405 by enabling designers to modify the TLB replacement algorithm to match application software requirements. System designers can make three key changes to give their products a competitive edge:

• Define page sizes to optimize memory allocation.
  
• Lock down regions of memory managed by the TLB to give preference to high-priority programs.
  
• Extend the TLB replacement algorithm to give preference to real-time programs.

Designers can mix high-priority real-time programs with lower-priority programs (for example Linux) and still maintain high response times for embedded applications by instituting these changes.

Extending functionality still further, the OnCore OS PowerPC 405 product enables the use of the SPRG registers unique to the 405 to improve performance. In addition, the internal Ethernet, DMA controllers, PCI Bridge, and other powerful integrated IPs are also fully supported by OnCore OS.

 
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