Roll the muffled drums. Haul out the black crepe. Close the coffin on the full custom ASIC and send it to its reward. Never mind that the corpse still appears to be twitching. The ASIC is dead. Gone the way of the dinosaur. Well, maybe not exactly the dinosaur-more like the coelacanth. It will live on in small numbers in the murky depths and occasionally be dragged up for the edification of the curious.

Like most species, the ASIC is not going extinct because of internal flaws, but because it cannot survive in a changing environment-an environment increasingly dominated by programmable logic. However, there are also other factors at work. These include increasing time-to-market pressures, shorter product lifecycles and just plain money. Once an attractive option for getting just the right functionality for a reasonable price, the custom ASIC will no longer be able to keep up with the alternatives. The cost of getting first silicon back has gone to well over a half a million dollars-a cost that must be amortized over volume in addition to the actual production costs of the silicon. And that's if there's no mistake in the incredibly complex design. We see the custom ASIC being driven to an ever-smaller number of very high-volume designs such as game consoles.

For the rest of the world, the name of the game is fast design turnaround, high performance, multiple product upgrades, shorter product life and volumes that can no longer sustain the up-front expense of developing an ASIC. The increased densities and performance of FPGA technology is offering an alternative that makes it hard for developers to resist. The emergence of programmable logic will not only spell the doom of the ASIC; it will also profoundly affect the way systems are designed.

Now that it is possible to implement established instruction set architectures such as ARM, MIPS and PowerPC on the same die as a very large programmable logic array, system-on-chip design is taking a new course. Only the pressures of extreme performance demands and high volume seem able to withstand the configurable alternatives. But it's not only in processor supported silicon that programmable logic is alluring. With the advent of myriad new interconnect technologies such as RapidIO, InfiniBand, PCI Express and HyperTransport, to name a few, FPGA solutions offer lower risk opportunities to get into the market quickly with leading-edge technology.

Even the volume argument for custom ASICs is beginning to fall apart, mostly due to the increased up-front design costs. A company that implements a prototype design on an FPGA and then goes into initial production with that same solution might, in the past, have considered lowering production costs by moving to an ASIC if sales volumes grew sufficiently. The lower unit costs of the ASIC would justify such a move. However, I have to believe that today the FPGA companies can play the volume discount game as well. The cost barrier to moving to a custom ASIC has risen that much.

If you move from a working FPGA-based solution to an ASIC, you still have to pay the up-front costs for first silicon. Today, it might be advantageous to work out a volume deal with the FPGA vendor to simply supply pre-programmed parts in volume. The unit cost would of course be more than that of production ASICs but with the logic development already done, it might be a cost advantage over using the lower ASIC cost to make up the NRE expenses.

The deeper implications of programmable logic for system development, however, lie in what it means for the development process. Hardware design will be forged by the definition of functionality in software. While there will still be plenty of room for traditional processors and standard parts, tools that define the FPGA's role will express their function as software or as parameters of a function such as a filter, several layers of abstraction above the actual hardware. Nobody will wish to or need to work in languages like Verilog or RTL. In fact, the lowest level of abstraction most folks will have to deal with should only be at the logic gate level: AND, NAND, OR, etc. The rest of us will work at levels higher than this.

This will mean a new generation of tools and the education of engineers. Systems will increasingly consist of hard-wired processor cores either on the same die with FPGA arrays-and by the way with programmable analog arrays-or interacting with programmable logic on separate parts and, of course with off-the-shelf silicon. The software will be a mix of traditional code, code that invokes functions in the logic, and code that dynamically changes the function of the logic. As Bette Davis said, “Fasten your seatbelts. It's going to be a bumpy night.”

Tom Williams is Editor-in-Chief of RTC Magazine.

This column, which originally appeared in the August 2002 edition of RTC Magazine, is copyright © 2002, The RTC Group. Reproduced by LinuxDevices.com with permission of The RTC Group.

 
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