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Startup claims its CMOS tech cuts power consumption by half

Jun 7, 2011 — by LinuxDevices Staff — from the LinuxDevices Archive — 1 views

A newly unveiled startup says it has devised a CMOS platform that can cut the active power consumption of “a wide range of integrated circuit products” by half, and leakage power consumption by up to five times. SuVolta says its “PowerShrink” platform has already been licensed by Fujitsu, which will offer it in 65nm products in 2012.

SuVolta, a six-year-old company that came out of stealth mode June 6, is introducing its PowerShrink platform, which officials said reduces power consumption through new transistor technology called Deeply Depleted Channel (DDC) CMOS technology. The PowerShrink platform also includes DDC-optimized circuits and design techniques, all of which together helps drive down voltage by up to 30 percent or more, greatly reducing power consumption.

At the same time, SuVolta's technology also reduces power leakage by 80 percent or more, maintains a chip's performance, and does not increase production costs, the company claims. Officials said the PowerShrink platform can be used for a variety of IC (integrated circuit) platforms, including chips, SRAMs (static random-access memory) and SoC (system-on-a-chip) architectures.

SuVolta's technology, which officials said should go into production in 2012, comes as chip-makers Intel and Advanced Micro Devices are driving down the power consumption of their x86-based processors as they look to gain a share of the red-hot mobile chip market. The mobile market is currently is dominated by ARM Holdings-designed chips from such vendors as Samsung, Qualcomm, Texas Instruments, and Nvidia.

"Power consumption has become the limiting factor in the amount of functionality that can be packed into mobile computing devices like smartphones, tablets and notebooks," Bruce McWilliams, president and CEO at SuVolta, said in a statement. "Lowering semiconductor power consumption has far-reaching benefits for the range of applications and products that can be developed."

SuVolta's DDC CMOS technology, with its unique channel structure, essentially reduces the electrical variation of the threshold voltage of the chip's transistors. This helps drive down power consumption, which officials said is crucial when scaling chip process technologies and adding features.

"The biggest problem in semiconductors today is not performance but power," SuVolta CTO Scott Thompson stated. "SuVolta is solving the power impasse by significantly reducing transistor threshold voltage variation and therefore enabling supply voltage scaling. SuVolta's DDC sub-micron technology addresses threshold voltage control by limiting random and other sources of dopant fluctuation while simultaneously improving carrier mobility and reducing device capacitance so as to maintain circuit speed at much lower power."

At the same time, SuVolta's platform can be used with current CMOS design rules and process flows, according to company officials. This helps keep production costs down because the platform can be built using existing fabs, and won't require chip manufacturers to invest in new fabs or equipment. By comparison, Intel is expected to spend millions of dollars to upgrade its fabs to produce chips with its new 3D Tri-Gate transistor technology, which the giant chip maker introduced in May.

SuVolta is looking to license its technology to chip-makers. Fujitsu Semiconductor is the first manufacturer to license the technology. The two companies have begun joint development in the push to commercialize the technology, SuVolta officials said.

Dr. Haruyoshi Yagi, corporate senior executive vice president at Fujitsu Semiconductor, stated, "Working closely with SuVolta on the joint technology development, Fujitsu Semiconductor has produced favorable results for reducing power consumption. By combining the SuVolta technology with our mature low-power process technology, Fujitsu Semiconductor will be able to aggressively respond to customers' requests for low-power consumption in consumer products and mobile devices."

The SuVolta team has got some deep industry experience. Thompson, the CTO, spent 12 years at Intel as a Fellow working on chip production processes. McWilliams, the CEO, had led Tessera Technologies, which also develops and licenses technologies for new electronic devices.

The 45-person company, which received $22 million in funding in 2010, is backed by the venture capital firm Kleiner Perkins Caufield & Byers. One of the firm's partners is Sun Microsystems co-founder Bill Joy, who also sits on the SuVolta board of directors.

Joy said in a statement, "SuVolta's PowerShrink platform can greatly reduce the power consumption of digital ICs, a $130 [billion] market. This will enable straightforward power reductions in existing ICs and libraries, and even greater improvements in new, and more aggressive designs which use additional capabilities of the SuVolta PowerShrink platform."

Availability

According to SuVolta and Fujitsu, PowerShrink will be initially available in the second half of 2012, in 65nm Application-Specific Standard Product (ASSP), Application Specific Integrated Circuits (ASIC), and Customer Owned Tooling (COT) products. An overview of the technology can be found on the SuVolta website.

Jeffrey Burt is a writer for eWEEK.


This article was originally published on LinuxDevices.com and has been donated to the open source community by QuinStreet Inc. Please visit LinuxToday.com for up-to-date news and articles about Linux and open source.



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