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Linux kernel port targets multi-core DSP SoCs

Apr 29, 2010 — by Eric Brown — from the LinuxDevices Archive — 10 views

Texas Instruments (TI) announced Linux kernel support for its TMS320C64x multi-DSP core system-on-chips (SoCs). Code Sourcery, Enea, Nash Technologies, and PolyCore have signed up to support the Linux port with, respectively, multi-core ready compiling and debugging tools, telecom middleware, inter-processor communications and LTE support, and MCAPI framework code, respectively, TI says.

The Linux kernel support will enable faster and easier software development in signal-processing intensive multi-core applications, says TI. Initially available for the TMS320C6472, TMS320C6474, TMS320C6455, and TMS320C6457 multi-core digital signal processor (DSP) SoCs in the third quarter, it targets applications such as communications and mission critical infrastructure, medical diagnostics, plus high-performance test and measurement, says the chipmaker.

TI has already rounded up a number of software partners to assist in its effort to port the Linux kernel to the C64x ISA (instruction set architecture). The project's goal is to encourage and the Free Software Foundation to accept the C64x Linux kernel and Code Sourcery's supporting GCC/GDB tools, making both fully supported as open source community projects, says TI. In addition, TI will sponsor a Linux-C64x portal and a community-oriented distribution program.

TI's C64x Linux kernel project partners are said to include:

  • Code Sourcery — The programming tools firm is developing a complete tool chain for the C64x SoCs, including support for the GNU Compiler Collection (GCC) and the GNU Project Debugger (GDB).
  • Enea — The Swedish telecom firm is making its open source, scalable multi-core communications stack available to the C64x Linux community, as well as offering multi-core platform software and debugging tools, says TI. Here, the company appears to be referring to Enea's Linux-ready Enea Accelerator Platform telecom suite, based on its high-availability Element middleware.
  • Nash Technologies — This German telecom software firm is implementing a variety of features for the port, "ranging from advanced chip level functions, such as multi-core interprocessor communications, to complete LTE protocols," says TI.
  • PolyCore Software — This Burlingame, Calif. firm, which specializes in multi-core development software, is implementing the MCAPI (Multicore Communications API) framework for the port.

TI's C64x+ SoCs

The TMS320C64x+ SoCs are the highest-performance multi-core DSP processors in the TMS320C6000 DSP family, says TI. Based on a third-generation VelociTI very-long-instruction-word (VLIW) architecture, they include multiple instances (typically three) of the same C64x processor core.

These are the same C64x cores found in TI's ARM-core enabled DaVinci processors, such as the recently announced TMS320DM8168. The C64x cores are also found in many of the TI's ARM Cortex-A8 enabled OMAP3x SoCs, such as the OMAP3530. With the new port, then, system designers developing signal-intensive equipment can take full advantage of the DSP cores directly with Linux, without requiring a SoC that also includes an ARM core.

TI's top-of-the-line TMS320C6474 block diagram
(Click to enlarge)

Based on 65nm process technology, the most powerful version of the four SoCs — the C6474 model — combines three C64x cores, which are available with up to 1.2GHz clock rates. The SoC (block diagram above) is thus capable of delivering 3.6GHz of total raw DSP processing power with performance of up to 28,800 million instructions per second (MIPS), claims TI.

Each C64x+ DSP core incorporates eight functional units, two register files, and two data paths. As with the earlier C6000 devices, two of these functional units are multipliers, doubling the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs) every clock cycle, says the company. As a result, eight 16-bit x 16-bit MACs are said to be executed every cycle on the C64x+ core, or 9600 16-bit MMACs every microsecond.

The C6474 SoC, which was announced in 2008, integrates on-chip memory organized as a three-level memory system, with the level-1 data memories on the device allocated at 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two, says TI.

In addition the C6474 also provides two coprocessors — the enhanced Viterbi decoder coprocessor (VCP2) and the enhanced turbo decoder coprocessor (TCP2) — for upchannel-decoding operations, says TI. The C6474 offers a gigabit Ethernet MAC, dual Serial RapidIO (SRIO) interfaces, and I2C. Other peripheral support is said to include dual multi-channel buffered serial ports (McBSPs), 16 GPIO, and six 64-bit general-purpose timers.

Stated Olaf Soentgen of Nash Technologies, "TI's C64x processors have an enviable footprint in signal processing oriented high-performance multicore applications, The introduction of Linux support expands the utility of the C64x into portions of these applications that traditionally have been reserved for RISC cores. We are taking advantage of Linux availability on TI's SoC to lower the cost and simplify the development of femtocell base stations."

Stated Brian Glinsman, GM of TI's communications infrastructure business, "Our customers are rapidly moving towards open source as a critical element of their solutions. Because of the C64x-based products' ultra low power consumption and cost effectiveness, customers are interested in running traditional DSP MAC/PHY and codec algorithms as well as classic RISC control code and protocols on our DSPs. TI's embracing of Linux and an open tool chain for the industry workhorse C64x makes this kind of integration practical."


Product support for the C64x Linux kernel will be available for TI's C64x in the third quarter, says the company. More information may be found on the TMS320C6472 here, the TMS320C6474 here, the TMS320C6455 here, and the TMS320C6457 here.

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