San Jose, CA; Microprocessor Forum — (press release excerpt) — MIPS Technologies, Inc. today announced a series of new enhancements to its popular MIPS32 and MIPS64 microprocessor RISC architectures. The new enhancements will increase processor efficiency and performance while cutting system power and costs in future implementations. As the foundation for next-generation MIPS-based processor-related development, the enhanced architectures will support all legacy IP (intellectual property) and will be fully compatible with the extensive lineup of third party tools, operating systems (OSs) and application software supporting the MIPS architecture.

The new architectural enhancements include . . .

• Reduced interrupt latency including faster and more efficient interrupt processing and new support for vectored interrupts
  
• Enhanced bit-field manipulations
  
• Enhanced coprocessor support
  
• Expanded memory management unit (MMU)
  
• Enhanced control of caches

The new architectural enhancements will simplify and standardize the underlying mechanisms that will be used in supporting real-time software, assuring the continued availability and investment protection of standard development tools, operating systems and applications for MIPS-based solutions. This also will lower costs and speed the development of new tools for the MIPS processor market. Read full announcement

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