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NEC unveils dynamically reconfigurable processor architecture

Oct 16, 2002 — by LinuxDevices Staff — from the LinuxDevices Archive — 2 views

San Jose, CA; Microprocessor Forum — (press release excerpt) — NEC unveiled a new architecture for dynamically reconfigurable processor LSI solutions at the annual Microprocessor Forum held this week in San Jose, CA. During its presentation, NEC revealed the company has successfully developed a prototype LSI solution that can be configured instantaneously to meet the dynamically changing requirements of… system designs. The new class of system LSI solutions, with easily customizable specifications, is designed to address the shorter commercial life of today's systems and the time-to-market pressures faced by system designers. The new architecture, to be offered in dynamically reconfigurable processor-based application specific standard products (ASSPs) as well as intellectual property (IP) cores, is designed to support the packet processing operations of network devices, such as high-end switches and routers. The dynamically reconfigurable processor LSI devices are also designed for use in applications requiring image and signal processing.

During the dynamically reconfigurable processor architecture technology session at Microprocessor Forum, NEC provided details on the new Linux-based design tool that automatically generates the optimum circuit layout from application information described in C language. Part of the tool suite is a new compiler and software flow to implement dynamically reconfigurable processor architecture-based designs. Based on an in-house, high-level synthesis tool called Cyber, the compiler generates FSM and associated datapath planes from C-level source code. A mapper maps Verilog register transfer levels (RTLs) for each datapath plane to individual PEs and memory devices. Finally, a new place and route tool physically locates the PEs and memory devices to mutually connect them.

 
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