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The history, technology, and potential of PCI Express

Nov 10, 2004 — by Henry Kingman — from the LinuxDevices Archive — views

Via Arena has published an article about PCI Express (PCIe) that discusses the new standard's history, technology, and market potential. PCIe radically increases PCI bus bandwidth, enabling support for multiple gigabit Ethernet interfaces, multiple SATA 150 drives, and next-generation graphics cards.

According to author Steven Walton, the original PCI bus was created in the early 90s, to replace the ISA bus. PCI includes two channels. One transmits data between connected devices and the system memory and CPU, while the other provides control, managing where the data is transmitted.

The PCI bus, when first rolled out in 486-class machines, operated at 33MHz, and was able to transfer 133MB/s. A 66MHz version and a 64bit/133MHz version called “PCI-X” later appeared, but never made it into the mainstream PC market, according to Walton. Thus, the system bus on many computers today can be saturated by a single ATA133 hard drive, Walton suggests.

In 2002, Walton says, a new standard called PCI Express (PCIe, formerly 3GIO) was developed by Microsoft, Dell, IBM, Intel, and others. PCIe is a serial interconnect technology that currently operates at 2.5GHz using just 0.8v. It is backward-compatible with PCI, enabling PCIe equipped motherboards to also provide PCI slots for legacy cards. However, PCIe provides a “huge leap” in bandwidth, Walton says.

According to Walton, a single PCIe “lane” operating at 2.5GHz can transfer 250MB/s in each direction. And, multiple lanes can be combined as needed. Most desktop boards will offer a few single-lane links, for peripherals such as RAID controllers, along with one or two 16-lane links for PCIe graphics boards. Via's K8T890 chipset supports 20 PCI-X lanes, for a total bandwidth of 10GB/s, Walton says.

Walton expects PCIe to proliferate first in I/O devices such as network cards wtih dual gigabit Ethernet ports, which are simply not possible to implement on PCI cards. PCIe will also complement SATA, which was limited when it first appeared by the PCI bus, until SATA support began appearing in southbridge chips. Both PCIe and SATA save PCB (printed circuit board) traces, due to their serial architecture, and both are excellent choices for small-form-factor devices (such as embedded systems).

PCIe has also started to appear in high-end graphic cards, based on a 164-pin connector supporting 16 lanes. This interface doubles the throughput of today's 8x AGP bus; however, 8x AGP has not yet become a bottleneck, and today's PCIe cards are simply ports of AGP card technology to the new form factor, Walton adds.

In conclusion, Walton writes, “The PCI Express bus creates room to breathe for a whole host of high bandwidth devices such as RAID controllers, Gigabit LAN controllers, video capture cards and so on.”

The complete Via Arena article is available here.


Also of interest . . .


Be sure to also read the “Introduction to PCI Express,” which provides Intel's perspective on the whys and wherefores of PCI Express, and where it's heading.


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This article was originally published on LinuxDevices.com and has been donated to the open source community by QuinStreet Inc. Please visit LinuxToday.com for up-to-date news and articles about Linux and open source.



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