The PCI-SIG (PCI Special Interest Group) says the next generation of its PCI Express I/O technology will run over copper at twice the speed of the current version. PCI Express 4.0 will move data at 16 gigatransfers per second (GT/sec.), according to the organization, which says the spec won't be finalized until at least 2014.

The PCI-SIG is an industry group formed in 1992 around PCI (peripheral component interconnect), the expansion bus technology that all but replaced the original ISA bus during the 90s. It first defined the PCI Express bus — a low-cost, high-performance I/O technology that's widely used in PCs and embedded devices — in 2002.

Now, the group says, "approximately 24 billion lanes of PCIe have shipped in the marketplace since its introduction," and transfer rates have steadily increased, too. On Nov. 28, it announced that it will be technically feasible to double the speed of PCI Express by 2014 or 2015.

According to the PCI-SIG, PCI Express 4.0 will:

• run at 16 GT/sec. over copper
• require approximately the same power as PCI Express 3.0
• be compatible with previous PCIe generations
• be feasible with "mainstream silicon process technology" and "existing low-cost materials"

According to an EE Times report, PCI SIG members spent six to nine months running simulations in order to see if 4.0 — expected to be the group's last copper-based spec — could be pushed to 24GT/sec. But Al Yanes, president of the group, is quoted as saying, "It became too technically challenging to achieve anything beyond 16G — 24G [would] blow out the jitter budgets, and you have to have enough margins to do this in high-volume manufacturing."

While the PCI-SIG might have settled on a data rate, bandwidth-hungry users will likely have to wait until 2016 to purchase PCI Express 4.0-equipped products. Many other details of the spec have yet to be worked out, meaning that "final PCIe 4.0 specifications, including form factor specification updates, are expected to be available sometime in the 2014-2015 timeframe," the group says.

Issues remain regarding active and idle power consumption, and there's reportedly also concern that any board using PCIe 4.0 over distances greater than ten to 12 inches will require re-driver chips. But, EE Times adds, the faster spec should ultimately save power, since current designs have to use multiple PCI lanes — with more wires and I/O pins — to meet their throughput needs.

Background

In August 2007, the PCI-SIG announced PCI Express 3.0 as the "next generation of PCI Express architecture," saying it would double bandwidth while offering backward compatibility. The new specification increased bus speed to 8GHz, compared to the 5GHz and 2.5GHz used by PCI Express 1.0 and 2.0, respectively.

PCI Express 3.0 also moved from the previous 8- and 10-bit data encoding schemes to 128-bit and 130-bit encoding, eliminating a 20 percent overhead. As a result of all this, it was claimed, PCI Express 3.0 gained an effective bandwidth of 7.99GT/sec., rather than PCIe 2.0's maximum of 4GT/sec.

Ultimately, the release of the PCI Express 3.0 spec was delayed by more than a year due to extensive backwards-compatibility testing. When the spec finally emerged in November 2010, the group noted that products based on it could achieve aggregate bandwidth approaching 32 GB/sec. on a sixteen-lane (x16) configuration.

MSI's Z68A-GD80, released last July, was claimed to be the first motherboard with PCI Express 3.0 expansion
(Click to enlarge)

The 32 GB/sec. speed is precisely what MSI claimed for the two PCI Express 3.0 x16 slots on the Z68A-GD80 motherboard (above) it released in July, with the obvious expectation that they'd be used by gamers to drop in discrete graphics cards. The motherboard can drive its HDMI and DVI-D video outputs using the integrated graphics on the supported "Sandy Bridge" Core CPUs, but Lucidlogix Virtu technology ensures that AMD or Nvidia graphics cards are invoked when applications would benefit from them, MSI added.

Meanwhile, the Thunderbolt interconnect announced by Apple and Intel last February combines PCI Express and DisplayPort signals into a serial data interface thanks to a special controller chip (pictured). Initial implementations run at 10Gb/sec. over copper, but the technology will eventually scale up to 100Gb/sec. optically, the companies say.

According to the EE Times report cited earlier, the PCI SIG has only one active effort on optical so far. A working group developing a cabled PCIe Version 3.0 specification that could compete with Thunderbolt has been charged with considering an option for an optical medium, the unbylined story says.

Jonathan Angel can be reached at [email protected] and followed at www.twitter.com/gadgetsense.

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