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ARM unveils next-gen, 2.5GHz Cortex-A15 processor

Sep 9, 2010 — by Eric Brown — from the LinuxDevices Archive — 18 views

ARM announced the licensing availability of a “Cortex-A15 MPCore” for processors that will run at up to 2.5GHz. Designed for devices ranging from smartphones to server, the Cortex-A15 targets 32nm and 28nm fabrication processes, and is touted as offering enhanced virtualization support, 1TB memory access, plus five times the performance of current smartphone processors — all with similar power consumption.

The Cortex-A15 MPCore targets system-on-chips (SoCs) for devices including smartphones, tablets, and large-screen mobile computing devices,. Also supported are more stationary systems such as digital home entertainment systems, wireless basestations, and enterprise infrastructure products, says ARM.

The Cortex-A15 first came to light in February when ARM briefly mentioned an upcoming "Eagle" design. Other reports at the time said the Eagle would offer multicore support, high-end graphics, and power usage that can be kept down by using Global Foundries' 28nm production process.

Last month, ARM offered more details about the Eagle, saying that it incorporated extensions to its ARMv7-A architecture, including hypervisor extensions and the ability to address up to 1TB of RAM. This dwarfs the 4GB limit for the Cortex-A9, which was announced in 2007, and has only recently found widespread use in system-on-chips (SoCs) such as the popular, dual-core Nvidia Tegra 2.

Like the Cortex-A9, but unlike the earlier, still widely used Cortex-A8, the Cortex-A15 is an MPCore processor, which means it offers interconnect technology that supports multicore designs. The Cortex-A9 is still being upgraded in an upcoming 28nm version that itself could reach 2.5GHz, although not, presumably with the same power savings touted for the Cortex-A15.

ARM's Cortex-A roadmap shows a 2012 debut for Cortex-A15 SoCs

(Click to enlarge)

The Cortex-A15 processor will be supported by specifically optimized ARM Physical IP that will enable 32nm and 28nm technologies, with a roadmap extending to 20nm, says ARM. Lead licensee partners who will make the first SoCs based on the Cortex-A15 are listed as Samsung, ST Ericsson, and as had been previously tipped, Texas Instruments, which will incorporate it in upcoming OMAP designs.

According to the roadmap above, we should see the first Cortex-A15 devices in 2012. While the Cortex-A15 is capable of 2.5GHz performance, ARM usage profiles suggest that most manufacturers of smartphones and other mobile devices will want to clock the processor from between 1GHz and 1.5GHz in single- or dual-core configurations for an optimal performance/power consumption trade-off.

The optimal suggested clock rate jumps to between 1GHz and 2GHz for home entertainment devices, and from 1.5GHz to 2.5GHz for embedded "Home and Web 2.0" servers, as well as wireless basestations.

Cortex-A15 block diagram
(Click to enlarge)

The Cortex-A15 MPCore processor is equipped with an out-of-order superscalar pipeline, along with a tightly-coupled low-latency level-2 cache of up to 4MB, says ARM. The processor can decode and dispatch up to three instructions per cycle, says the company. This is said to be three times the rate possible with an ARM11 processor.

In addition, the Cortex-A15 can issue up to eight instructions per cycle, and take less than 10 microseconds to move into standby or wake up again. Floating point and NEON instruction set performance for signal processing and multimedia have also been improved, says the company.

Compared to the Cortex-A9, the Cortex-A15 adds more efficient hardware support for operating system (OS) virtualization, soft-error recovery, larger memory addressability, and system coherency, says ARM.

For example, as ARM tipped last month, the A15 adds technology aimed at virtualization called Large Physical Address Extensions (LPAE). Shown in the diagram below, LPAE is said to address up to 1TB of memory. Also provided is improved error correction for fault-tolerance and soft-fault recovery.

LPAE will let ARM CPUs work with physical memory up to 1TB

(Click to enlarge)

The Cortex-A15 is claimed to be the first ARM processor to incorporate highly efficient hardware support for data management and arbitration. This hypervisor support enables multiple virtual software environments and their applications to simultaneously access system capabilities while remaining isolated from each other, says the company. (For more details on some of the virtualization-oriented features in the ARMv7 extensions, see our earlier coverage here.)

Hypervisor support available via ARMv7 extensions found in Cortex-A15

(Click to enlarge)

Like the Cortex-A8 and Cortex-A9, the Cortex-A15 is based on ARMv7-A architecture, and offers instruction sets including Thumb-2, TrustZone, and NEON (see below). The processor supports up to four symmetric multiprocessing (SMP) cores with a single processor cluster, and multiple coherent SMP clusters can be tied together via ARM's AMBA 4 interconnect technology, says ARM.

The Cortex-A15 offers the following key features, says ARM:

  • Thumb-2 — provides up to a 30 percent reduction in memory required to store instructions
  • TrustZone — security and digital rights management (DRM)
  • NEON — accelerates accelerate multimedia and signal processing algorithms
  • DSP and SIMD extensions — claimed to increase DSP processing performance while offering low power consumption
  • Floating point — increased performance and support for half-, single-, and double-precision floating point arithmetic
  • Jazelle RCT — provides up to 3x reduction in code size for Just-in-time (JIT) and ahead-of-time compilation of byte-code while supporting direct byte-code execution of Java instructions for acceleration in traditional virtual machines
  • Hardware virtualization — offers efficient hardware support for data management and arbitration
  • LPAE — offers access to up to 1TB of memory
  • Optimized Level 1 caches — optimizations for performance and power that combine minimal access latency techniques, supporting 32KB instruction and 32KB data caches, and offering optional cache coherence for enhanced inter-processor communication (IPC) and support for SMP-capable OSes
  • Configurable-size Level 2 cache controller — low latency and high bandwidth access to up to 4MB of cached memory in high frequency designs, or reduced power designs associated with off-chip memory access
  • Reliability and soft fault recovery — All RAM, including L1 and L2 caches, protected by parity and ECC error correction
  • AMBA 4 cache coherent interconnect (CCI) — provides AMBA 4 AXI Coherency Extensions (ACE) compliant ports for full coherency between multiple Cortex-A15 processors
  • Neon media processing engine (MPE) — combines both floating point and Neon instructions for further media and signal processing acceleration
  • Floating-point unit (FPU) — high-performance single, and double precision floating-point instructions compatible with the ARM VFPv3
  • Snoop control unit (SCU) — Manages interconnect, arbitration, communication, cache-2-cache and system memory transfers, cache coherence, and more, exposing such capabilities to system accelerators and non-cached, DMA-driven peripherals to increase performance and reduce power consumption
  • Accelerator coherence port — AMBA 3 AXI compatible slave interface on SCU, providing an interconnect point for masters that "are better interfaced directly with the Cortex-A15"
  • Generic interrupt controller (GIC) — IPC interrupt controller, for routing and prioritizing system interrupts, supporting up to 224 independent interrupts

The processor is said to offer full application compatibility with all other Cortex-A processors, thereby enabling access to software including Android, Linux (including Ubuntu), Microsoft Windows Embedded Compact 7, and Symbian operating systems. Compatibility is also claimed for Adobe Flash Player, Java Platform Standard Edition (Java SE), and JavaFX, among other applications.

In addition, the processor is supported by ARM technology including the AMBA 4 compliant CoreLink system IP, CoreSight debug and trace IP, Mali Graphics, and a wide variety of development tools, says the company.


In addition to the following quotes, testimonial quotes supplied for the Cortex-A15 were offered from Microsoft, Adobe, Cadence, Express Logic, Green Hills Software, Lauterbach, Linaro, Mentor Graphics, Open Kernel Labs, QNX, Symbian Foundation, Synopsys, VirtualLogix, and VMware.

Stated Mike Inglis, EVP and GM, processor division, ARM, "The Cortex-A15 MPCore processor will become the next major step along the industry's energy efficient computing roadmap and open up a wide range of new application possibilities for our Partners."

Stated Yiwan Wong, VP of SoC marketing, system LSI division, Samsung Electronics, "We believe this new Cortex-A15 MPCore processor core from ARM, with its quantum leap in processing capabilities, will successfully enable many next-generation electronic products and redefine the level of experience consumers will demand from their smartphones and mobile computing devices."

Stated Edgar Auslander, senior vice president, strategic planning at ST-Ericsson, "Following our pioneering single die integration of modem and application engine featuring a dual Cortex-A9 processor, we are pleased to continue to work with ARM as a lead partner for the Cortex-A15 MPCore processor."

Stated Remi El-Ouazzane, vice president, OMAP platform business unit, Texas Instruments (TI), "When pairing the Cortex-A15 MPCore processor with TI's SmartReflex 3 technology, future OMAP applications processors will yield a 60 percent reduction in power, enabling TI to continue delivering the industry's most energy-efficient, high-performing solutions."

A video highlighting ARM's Cortex-A15
Source: ARM Holidings
(click to play)


The Cortex-A15 MPCore processor design is now available for licensing, says ARM. Finished silicon is expected in 2012. More technical information may be found here, and an ARM blog announcement may be found here.

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