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Configurable ARM-powered SoCs target Linux devices

Mar 8, 2007 — by LinuxDevices Staff — from the LinuxDevices Archive — 2 views

STMicroelectronics (ST) is sampling a pair of configurable SoCs (system-on-chip processors) powered by ARM9 cores and 600K-gate configurable logic blocks. The SPEAr (structured processor enhanced architecture) Head600 and dual-core SPEAr Plus600 run Linux, support DDR/DDR2 external memory, and target printer, fax, and POS (point-of-sales) devices.

ST launched its SPEAr in October of 2005, with the release of the SPEAr Head200. That chip integrates a 266MHz ARM926EJ-S core with a 200K-gate configurable logic block. The new SPEAr Head600 and Plus600 chips use the same ARM925EJ-S core, clocked up to 333MHz. The Head600 has one such core, while the Plus600 has two. Both chips also integrate a 600K-gate reconfigurable logic array with 88 dedicated GPIOs, 9 LVDS (low-voltage differential signal) channels, and a 128KB pool of configurable internal memory.

ST SPEAr Head600 and Plus600
(Click each image to enlarge)

The dual-core SPEAr Plus600 supports multi-OS applications, such as multifunction printers and copiers, ST says. Linux or a similar complex OS can run on one processor, handling connectivity and system management, while an RTOS (real-time OS) on the second ARM9 core, handling timing-critical tasks such as motor control.

Additional features of both chips include:

  • Multilayer AMBA 2.0 compliant Bus with 166MHz fMAX
  • 32KB ROM
  • 8KB common SRAM
  • Dynamic power saving features
  • High performance 8 channels DMA
  • Ethernet 10/100/1000 MAC with GMII/MII Interface to external PHY
  • 1 x USB 2.0 Device port with integrated PHY
  • 2 x USB 2.0 Host ports with integrated PHY
  • External SDRAM memory interface:
  • Flash memory interfaces:
    • NAND 8/16-bit
    • Serial (up to 50Mbps)
  • 3-SPI Master/Slave up to 40Mbps
  • I2C Master/Slave mode — high, fast, and slow speed
  • 2 independent UART up to 460.8 Kbps with software flow control mode
  • IrDA (Fir-Mir-Sir), from 9.6Kbps to 4Mbps
  • Color LCD controller:
    • up to 1024×768 pixels
    • 24bpp “true color” TFT panel
    • 16bpp DSTN panel
  • 10 bidirectional GPIO lines with interrupt capability
  • 88 RAS-GPIO, user customizable bidirectional lines (up to 4 clocks)
  • ADC 10 bit, 1MSPS, 8 analog inputs
  • JPEG codec accelerator
  • 10 independent timers with programmable prescaler
  • Real time clock
  • Watch dog timer
  • System controller
  • Misc internal control registers
  • JTAG (IEEE1149.1) interface

Vittorio Peduto, GM of ST's Computer Systems Division, stated, “These products [offer] an unprecedented feature set, connectivity, and computing power, allowing them to address the full market from high-end to low- and mid-range models using the same architecture and software stack.”

The chips are fabbed on 90nm process technology. Their configurable IP block supports a variety of hardware accelerators, as well as connectivity IP (intellectual property) for fast IrDA, Gigabit Ethernet MAC, and three USB 2.0 ports (1 Device, 2 Hosts).


Development boards based on ST's SPEAr Head600 and Plus600 will begin sampling to high-volume OEMs this month, the company says. The Head600 is priced at $10, while the dual-core Plus600 will cost $12 in quantities of 20,000.

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