Tensilica has revised its configurable, extensible processor core for SoC (system-on-chip) design. Xtensa 6 supports tools that generate hardware designs and toolchains from C/C++ algorithms, the company says. The synthesizable, 32-bit RISC core also features 30 percent lower power, and a “no execute” bit for high-security embedded Linux designs.

Tensilica's Xtensa cores are based on a proprietary 32-bit core architecture with 16- and 24-bit instruction sets. These small instruction sets offer higher code density and require less power than 32-bit instructions, the company says, yet support powerful branch instructions such as combined compare-and-branch and zero-overhead loops, and bit manipulations including funnel shifts and field-extraction operations. An optional FPU (floating point unit) is available.

Xtensa 6 architecture
Xtensa cores are supported by Linux, and available with an Eclipse-based IDE aimed at providing a single, unified environment for both hardware and software development.

Auto-generated SoC designs and toolchains

Tensilica says the new Xtensa 6 core supports its XPRES compiler, which can generate verified RTL (register transfer level) hardware descriptions and toolchains from C/C++ algorithms. Users input the algorithm they wish to optimize, and the XPRES compiler determines which functions should be accelerated in hardware. It then generates the hardware description, along with an optimized compiler, in “less than an hour,” the company claims.

Tensilica says its Xtensa 6 core and XPRESS compiler allow rapid evaluation of area/speed/power trade-offs. C code portability is preserved, since a special compiler is generated for each configuration. Additionally, the approach eliminates the need to verify hand-generated hardware descriptions written in VHDL (very high-level design language) or Verilog, the company says.

The XPRES compiler also supports the company's top-of-range Xtensa LX core, giving Xtensa 6 users a hardware upgrade path that does not require software changes, the company claims.

Other new features

Besides its new support for the XPRES compiler, the Xtensa 6 dissipates 25-30 percent less power than the Xtensa V, Tensilica says. The improvements are the result of fine-grain gating, which powers down small processor sections when possible, along with coarse-grain gating, said to conserve power throughout larger chip sections, such as the cache.

Another new feature is support for an NX, or “no execute,” bit. NX allows the execution of processor instructions to be disallowed in specific areas of memory, and is similar to AMD's EVP (enhanced virus protection) and Intel's XD (execute disable) schemes, Tensilica says. NX requires virtual memory support, and thus requires the Xtensa 6's MMU feature. Tensilica says NX support will be incorporated in future versions of Linux.

VP of Marketing Steve Roddy said, “Xtensa 6 [and] our XPRES Compiler can create application-specific building blocks that can serve as either conventional control processors or as a suitable alternative to RTL-based hardware block design. This product automates time-and-resource intensive IC design steps, and adds programmability to the post-silicon design.”

Availability

Xtensa 6 is shipping now. Licensing fees for a single processor configuration with perpetual usage rights start at $350,000.

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