STMicroelectronics announced a new line of SoCs (system on chips) that will employ dual ARM Cortex-A9 processors. The SPEAr1300 product line will support fully symmetrical operation at up to 600MHz/core, include a DDR3 memory interface, and be manufactured using 55nm HCMOS (high speed CMOS) technology, the company says.

ST says its new SPEAr1300 architecture will form the basis of several SoCs "to be announced over the next several months." It's claimed the design offers "industry-leading performance in terms of DMIPS/MHz and power consumption/DMIPS ratios, in addition to cost efficiency and customizability advantages."

ST says the SPEAr1300 line will offer dual ARM Cortex-A9 processors, clocked at up to 600MHz per core, for an equivalent of 3000 Dhrystone MIPS. The SoCs will be manufactured in ST's low-power, 55nm HCMOS process technology, the company adds.

It's said the devices will include an integrated DDR3 memory controller plus a "full set of connectivity peripherals like PCIe, SATA, USB and Ethernet." The SPEAr1300 SoCs will target applications such as networking, thin clients, videoconferencing, NAS (Network-Attached Storage), computer peripherals, and factory automation, according to ST.

A block diagram of STMicroeletronics' SPEAr1300 architecture
(Click to enlarge)

ST says key features of the SPEAr1300 architecture (pictured above) will include:

• Dual ARM Cortex-A9 cores, running at 600MHz for 3000 DMIPS equivalent
• 64-bit AXI (AMBA3) bus network-on-chip technology
• DRAM and L2 cache with Error Correction Code (ECC)
• 533MHz 32-bit DDR3 memory controllers with ECC; 16-bit DDR2 also supported
• Accelerator coherence port
• Gigabit Ethernet
• PCIe 2.0 supporting 5GT/s (Gigatransfers/second)
• SATA II3 Gbit/s
• USB 2.0
• 256-bit key hardware encryption/decryption
• 1.3 million gates of configurable logic

Loris Valenti, GM of ST's computer systems SoC division, stated, "This new architecture for the SPEAr family builds upon the unrivalled low power and multiprocessing capabilities of the ARM Cortex-A9 processor core. Upcoming SPEAr embedded microprocessors will deliver an unprecedented combination of processing performance, memory throughput, flexibility and low power for next-generation connectivity appliances."

Background

STMicroelectronics (ST) launched its SPEAr (structured processor enhanced architecture) range in 2005 with the release of the SPEAr Head200 , integrating a 266MHz ARM926EJ-S core with a 200Kgate configurable logic block. The SPEAr Head600 and SPEAr Plus600 followed in 2007, using the same core and 90nm production process, but clocking up to 333MHz and sporting a 600Kgate configurable logic array.

In 2008, ST moved to a 65nm process with the SPEAr Basic, again with the 333MHz ARM926EJ-S core. This time with a 300Kgate logic array, the device was touted as facilitating custom design, thanks to a separately available development kit and an external FPGA (field programmable gate array).

In February of this year, the company added the SPEAr300, 310, 320, and 600, using the same ARM926EJS core and similar clock speeds — 333MHz "worst-case," or "up to 400MHz" in typical conditions. Fabbed with 90nm and 65nm technology, too, the SoCs omitted configurable logic arrays, instead providing on-chip functionality tailor-made for different market segments. (For more details, see our earlier coverage, here.)

Availability

Operating system support was not detailed for the SPEAr1300, and we noted mention of only Linux for this year's SPEAr300, 310, 320, and 600 SoCs. However, earlier SPEAr offerings were also said to support Windows CE.

ST does not yet appear to have a product page devoted specifically to the new SPEAr1300 family. General information on the company's existing SPEAr SoCs may be found here.

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