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Cost conscious “real-time” ARM core runs uClinux

May 15, 2006 — by LinuxDevices Staff — from the LinuxDevices Archive — 81 views

ARM has released a new processor core aimed at mobile phones, hard-drives, printers, automotive designs, and other deeply embedded, highly “real-time” applications. The Cortex-R4 core has been validated with uClinux, MicroC/OS, and ThreadX, and was designed for high performance, high performance-per-cycle, on-chip memory cost containment, configurability, and high reliability, according to the… company.

The R4 targets relatively deeply embedded systems that are “cost-sensitive, highly real-time, and potentially now quite high-performance,” according to Richard York, ARM CPU product manager. York says high performance is in demand among deeply embedded chip customers, especially if it can be achieved without an increase in processor clock speed.

ARM R4 function block diagram
(Click for additional descriptives)

Because the R4 does not offer a memory management unit (MMU), it can not run standard Linux. However, it can instead run uClinux, a form of Linux that does not require an MMU, and has been validated for uClinux compatibility, according to York.

As an example of a typical R4 application, York cites automotive brake-enhancement systems, noting that Linux would not be used in such a system. “Basic ABS, or anti-lock braking can be done in 40-45MHz. ESC, or electronic stability control, requires an order of magnitude more performance, while maintaining the same area and power requirements.”

Mobile phones represent another potential market with high performance requirements, York says. He expects to see the R4 used in phone baseband processors, and in “single-chip” phone chipsets. “There's no reason why a 3G phone based on the R4 couldn't be running some reasonable user applications, as well as the protocol stack,” he said.

An R4 core can clock to 400MHz in two square-millimeters of silicon on 90nm TSMC (Taiwan Semiconductor Manufacturing Company) process technology, when used with cell, RAM, and cache components from ARM's “Artisan” family of IP (intellectual property), according to York. Additionally, the R4's “limited superscalar pipeline with branch prediction” enables it to deliver 1.62 DMIPS/MHz (millions of instructions per second per clock cycle, using Dhrystone benchmarks). This betters MIPS's 4K architecture by 16 percent, its 24K by 12 percent, and Tensilica's 570T by six percent, according to ARM figures.

Besides performance, memory cost containment is in demand, because memory “dominates the cost” of chips in deeply embedded markets, York adds. Thumb2 instructions help here, since increased code density requires less memory; Thumb2 code can be up to 30 percent smaller, and 22 percent faster, when starting with ARM9 code, York says. Thumb2 is supported by ARM's compilers, and ARM has contracted Code Sourcery to contribute support to GNU tools.

Another R4 feature aimed at containing memory costs is “relaxed” 2-cycle local memory access. This allows the processor to support slower memories, which are less costly and leaky, and more dense than high-speed memories, according to York. The R4 also integrates support for memory fault tolerance. “Memories are increasingly unreliable, and are the largest source of soft-errors. Parity and ECC are required for many applications,” York notes.

Additional touted R4 features and benefits include:

  • Enhanced debug interface, for easier multicore debugging
  • Healthy ecosystem — “The R4 has more support at this stage of its development than any ARM processor ever has,” according to York
  • Energy efficiency — ARM claims 6000 DMIPS per Watt
  • High density — Sizes as small as 0.86 square millimeters, and 180 gates, at slower clock speeds
  • AMBA on-chip bus
  • Optional “MPU” (memory protection unit) that — while it can not translate addresses like an MMU — can be used to protect peripherals and processes from one another, for example to integrate high- and low-speed devices on the same bus
  • Redundant core interface for error detection in safety-critical systems
  • 0, 1, 2 or 3 physical memories, grouped as 1 or 2 logical memories, which avoid the need to decide on instruction/data TCM split early in the design cycle

York says ARM has already licensed the R4 core to three lead customers, one of which is Broadcom. Broadcom's VP of R&D, Ed Frank, stated, “Broadcom's design teams have been working with ARM [on chips for] next-generation storage, networking, and mobile devices. The Cortex-R4 will bring significant performance and functionality benefits.”

John Cornish, VP of marketing for ARM's processor division, stated, “The embedded market is evolving rapidly as systems become more sophisticated, and software workloads increase. The Cortex-R4 gives chip designers unparalleled capabilities for the development of 3G phones, hard-disk drives, imaging, and automotive systems.”


ARM's “Cortex” brand replaced its ARM 7, 9, 10, 11 branding scheme about two and a half years ago. Availability of the R4 means that processors are shipping from each of Cortex's three sub-brands, which include:

  • High-end A-series (application) processors
  • Mid-range R-series (real-time) processors that support ARMv7 class instructions, in addition to Thumb2 instructions,
  • Low-end M-series (microcontroller) processors, roughly corresponding to ARM7, but supporting “Thumb2” rather than Thumb instructions

ARM announced its Cortex chip line in October, 2004, along with availability of an M3 core. It demonstrated the ARMv7 architecture at last year's Embedded Systems Conference, and shipped the Cortex A8 last Fall.


The ARM Cortex-R4 processor core is available for licensing now, at undisclosed prices. Also available to “lead and existing licensees, and for general release on request” are an Instruction Set Simulator (ISS) and ARM's just-updated RealView Development Suite, which supports the Cortex-R4.

Additional currently available complementary technologies for implementing full SoCs include the AMBA 3 AXI Interconnect (PL301), Configurable Dynamic Memory Controller (PL340), Static Memory Controller Family (PL350), and L2 Cache (L220).

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