Linux-ready 32-core SoCs offer real-time power optimization
May 12, 2010 — by Eric Brown — from the LinuxDevices Archive — 20 viewsCavium Networks announced new versions of its Octeon II family of multicore system-on-chips with between 8 and 32 MIPS64 cores. Supported by a Linux SDK, the Octeon II CN68xx/67xx SoCs are equipped with 85 L3-L7 application and security acceleration engines, virtualization features, 100Gbps of connectivity, and new “real-time” power-optimization technology, says the company.
The Octeon II CN68xx will be offered in 16, 24, and 32-core options, and will be pin and software compatible with the CN67xx, which will be offered in 8, 12, and 16-core options, says Cavium. Both processor families will sample in the fourth quarter, says the company.
The top-of-the-line, 32-core CN6880 version of the CN68xx delivers up to 48GHz of total compute power, with up to 40Gbps throughput processing, or up to 100Gbps when ganging multiple SoCs, claims Cavium (see farther below for a chart detailing all six CN68xx/67xx SoCs). The company does not appear to list what type of fabrication process is used for the SoCs.
The CN68xx/67xx SoCs are software compatible with the first Octeon II SoCs, which were announced in April 2009, and which were set to ship in 4Q 2009. Compared to the earlier Octeon Plus family, the initial two- to six-core CN63xx processors did not expand the core count (the Octeon Plus goes to 16 cores), but they did add a number of features designed to keep up with the demands of new media-centric 3G/4G networks, which Cavium refers to as "hyper networks."
Octeon II novelties included 75 application acceleration engines, power optimization components, and virtualization technologies. These features carry through to the new models except there are now said to be 85 acceleration engines.
Octeon II CN68xx block diagram. The CN67xx diagram is identical except for having fewer cores and only two Hyper Access Memory Controllers instead of four
The CN68xx/67xx SoCs target application acceleration for borderless enterprise, mobile internet infrastructure, and secure data center and cloud computing applications, says Cavium. Specific devices that could incorporate the SoCs include routers, switches, appliances, 3G/4G wireless base stations, RNCs, xGSNs, evolved packet core, services gateways, DPI equipment, storage switches, and intelligent server adapters, says the company.
Octeon II CN68xx/67xx in typical deployments: Services/ATCA blade (left) and networking/security appliance (right)
(Click to enlarge)
In addition to providing more MIPS64-bit cores, the key enhancement compared to the Octeon II CN63xx appears to be the new Real Time Power Optimizer (RTPO). This power optimization unit dynamically adjusts power depending upon the application-level processing requirements, says Cavium.
The RTPO can dynamically adjust per-core effective-frequency in real time, based on application or network-level workload, resulting in lower power consumption, says the company. In addition, a "fine-grained" auto power-down capability is said to be capable of switching off unutilized coprocessors and I/O interfaces.
cnMIPS64 v2 cores and HyperConnect Cross-Bar
The superscalar cnMIPS64 cores used in the CN68XX/67XX SoCs appear to have been upgraded to a "v2" version. Each SoC holds 8, 16, 24, or 32 of these cores, each with 37KB I-cache and 32KB D-cache, clocked at up to 1.5GHz, for a total of up to 48GHz of standard-ISA based processing power, says Cavium. In addition, the cnMIPS v2 cores deliver up to 2.5 times the control plane performance per-core vs. Octeon Plus, claims the company.
The SoCs connect to up to 4MB of partition-able, low-latency L2 cache via a "HyperConnect Cross-Bar," claimed to offer over 6Tbps of throughput. The architecture is said to offer lower-latency and more deterministic performance compared to ring or mesh architectures. The HyperConnect is said to link to independent I/O and coprocessor networks on the SoC (see block diagram farther above).
Accelerators and security
The CN68XX/67XX SoCs are equipped with 85 application and security acceleration engines that support L3-L7 networking, says Cavium. Accelerators, application- and security specific engines, as well as related processing functionality are said to include:
- 40+ Gbps of packet processing and TCP performance
- 40+ Gbps IPsec, SSL Security performance
- WAPI support in encryption/ decryption engines to support China-specific WLAN deployments
- Snow3G hardware acceleration for 4G security requirements
- Compression/decompression acceleration, with up to 20Gbps throughput
- Third generation HFA DPI engines for deterministic throughput of up to 15Gbps, independent of number of rules or flows
- Multicore hardware load balancing, scaling, and packet ordering, enabling linear performance scalability across 32 cores
Memory and interfaces
The CN68xx/67xx SoCs integrate up to four 72-bit ECC-protected DDR3 interfaces with 400+ Gbps of bandwidth, says Cavium. Networking interfaces are provided for SGMII, RXAUI, XAUI, and double-rate XAUI, supporting up to 12x gigabit Ethernet (GbE), 4x 10GbE, and 2x 20GbE Ethernet connections, says the company.
In addition, the SoCs are said to provide Interlaken or Interlaken-LA controllers with up to eight lane widths, providing a channelized interface. This is said to support up to 40Gbps of general bandwith, or can be used for coprocessor connectivity. Finally, the CN68XX/67XX provides dual PCI Express Gen2 controllers, with widths of up to eight lanes.
CN68xx models
(Click to enlarge)
CN67xx models
(Click to enlarge)
The new Octeon II SoCs are supported by the existing Octeon II Software Development Kit (SDK), which includes a Linux SMP implementation, as well as GNU toolchain, profiling, simulation, and optimization tools, says Cavium. Specific components are said to include GCC, GDB, DDD, Viewzilla, Perfzilla, and Oprofile (performance tuning). Optimized C libraries are said to be supplied for security, regular expression, and de/compression processing offload.
The SDK is said to offer a Simple Executive for fast-path or bare-metal applications, as well as APIs for hardware acceleration, and extensive sample applications. Development toolkits are also available for TCP/IP, IPsec, SSL, SSL-VPN, and Deep Packet Inspection (DPI), says the company.
Cavium's Multicore Partnership to Accelerate Customer End-Solutions (PACE) ecosystem supports Octeon II processors with over 50 technology partners, says the company. The partners provide operating systems and tools, software applications and stacks, debuggers, complementary silicon, ATCA and hardware appliances, hardware and software consulting, and other products and services.
Linux development partners include Wind River, and Cavium's own subsidiary, MontaVista Software, LLC. The latter announced specific support in MontaVista Carrier Grade Edition (CGE) Linux for the new processors.
Statements
Stated Dan Cauchy, VP of marketing and business development at MontaVista, "The Octeon II processor family provides the performance and power to enable innovative new applications in areas such as networking, VoIP, 4G/WiMAX and security."
Stated Linley Gwennap, Principal Analyst at The Linley Group, "Through its Octeon processor line and an impressive set of customer wins, Cavium has been the fastest growing embedded processor vendor over the last few years."
Stated Anthony Ambrose, VP and GM, Communication Networks, RadiSys, "We are pleased to see the significant increase in compute density, throughput and service features of the new Cavium CN68XX Octeon II processors."
Stated Matt Medeiros, CEO of SonicWall, "The Octeon II CN68XX will enable us to scale to 1024 cores and achieve well over 100Gbps of full malware protection so customers no longer have to compromise performance for security."
Availability
The Octeon II CN68xx and CN67xx processor families will start sampling in the fourth quarter. More information on the Octeon II CN68xx processors may be found here, and more on the CN67xx should be here.
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