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MIPS-like SoCs offer up to 100 cores

Oct 26, 2009 — by Eric Brown — from the LinuxDevices Archive — 14 views

Tilera Corp. announced a new family in its Linux-ready “Tile” line of massively multi-core system-on-chips (SoCs), including a model touted as “the world's first 100-core processor.” The 40nm-fabricated Tile-Gx family features a new 64-bit core and DDR3 memory controllers, and includes 16-, 36-, 64-, and 100-core models.

Tile-Gx processors are aimed at enterprise networking, cloud computing, multimedia, and wireless infrastructure, says Tilera. As with previous Tile processors, each "tile" (core) can independently run a full operating system, or multiple tiles can together "run a multiprocessing OS like SMP Linux," says the company. The Tile-GX provides performance-per-watt efficiency that's up to ten times better than Intel's next-generation, 32-nm Westmere processor, claims Tilera.

The Tile-Gx36 processor will be first out of the gate, sampling in Q4 of 2010. The Tile-Gx16, Tile-Gx64, and Tile-Gx100 will follow in the first half of 2011, says the company.

Tile-Gx100 architecture

Tilera announced its Tile64 family in August 2007, and announced the TilePro, a second generation version of the MIPS64-like SoC, in September of last year. The TilePro family includes a 36-core TilePro36 and 64-way TilePro64, both fabbed on 90nm process technology. In December, Tilera began shipping the TilePro36, which is aimed at graphics-intensive embedded applications and networking devices.

Moving to TSMC's 40-nanometer (nm) process, the Tile-Gx processors can be clocked at up to 1.5GHz, with the exception of the 16-core version, which tops out at 1.25GHz, says Tilera. The SoCs offer power consumption ranging from 10 to 55 Watts, claims the company.

Like the TilePro, the Tile-Gx is equipped with Tilera's two-dimensional iMesh interconnect technology, which is said to eliminate the centralized bus intersection that limited scalability in previous multi-core designs. It also shares with the TilePro a Dynamic Distributed Cache (DDC) feature, which acts as an on-chip communication network dedicated to cache management. DDC is said to enable the processors to double both the L1 cache size and L2 cache associativity, according to the company.

In addition to supporting a greater number of cores, the Tile-Gx is said to offer several major enhancements compared to the TilePro, including:

  • Next-generation 64-bit core — A new three-issue 64-bit core offers a full virtual memory system. Each core includes 32KB L1 I-cache, 32KB L1 D-cache, and 256KB L2 cache, with up to 26MB total L3 coherent cache available across the device, says Tilera.
  • Enhanced SIMD instruction extensions — A 4-MAC/cycle multiplier unit delivers up to 600 billion MACs per second signal processing performance, claimed to be more than 12 times the fastest commercial DSP.
  • DDR3 memory controllers — Two or four 72-bit controllers are available, running at up to 2133MHz speeds with ECC support. The chips support up to 1TB total DDR3 capacity, as well as "powerful memory striping modes for maximum utilization," says the company.
  • Hardware acceleration engines — An on-chip MiCA (Multistream iMesh Crypto Accelerator) system is touted as delivering up to 40Gbps encryption and 20Gbps full duplex compression processing, "tightly coupled to the iMesh for extremely low latency and wire-speed small packet throughput." Meanwhile, a true random number generator (RNG) and public key accelerator are said to enable up to 50,000 RSA handshakes per second.
  • mPIPE packet processing accelerator — The mPIPE (multicore Programmable Intelligent Packet Engine) system offers wire-speed packet classification, load balancing, and buffer management functions, says Tilera. The C-programmable engine is said to delivers 80Gbps and 120 million packets-per-second of throughput for packets with multiple layers of encapsulation.

Peripheral support is said to include up to eight 10GbE XAUI interfaces, two Interlaken interfaces, and three "Gen2" PCI-Express interfaces, each selectable as endpoint or root complex. The Tile-Gx processors are also said to offer up to 32 gigabit Ethernet MAC interfaces. The two higher-end versions come in 34 x 45mm BGA packages, while the two lower-end models ship with 35 x 35mm BGA packages.

Linux-based MDE development kit

As with previous Tilera processors, the Tile-Gx is supported by its Linux- and Eclipse-based Multicore Development Environment (MDE). In May of this year, Tilera released version 2.0 of the MDE, featuring an updated SMP (symmetrical multiprocessing) Linux implementation, optimized compilers, and enhancements to other development tools, according to the company.

New MDE features include a Bare Metal Environment (BME) run-time environment in addition to its pre-existing full SMP Linux implementation. Version 2.0 also provides a new Zero Overhead Linux (ZOL) that is said to "combine the best of both worlds" of the SMP and BME environments. There is also a new hybrid mode that lets developers mix and match two or three of these run-times on a single SoC.

Stated Omid Tahernia, Tilera's CEO, "The launch of the Tile-Gx family, including the world's first 100-core microprocessor, ushers in a new era of many-core processing. Customers will be able to replace an entire board presently using a dozen or more chips with just one of our Tile-Gx processors, greatly simplifying the system architecture and resulting in reduced cost, power consumption, and PC board area."

Stated Sergis Mushell, principal research analyst, Gartner, "Cloud computing and virtualization have ushered in a new era of processing power optimization and utilization, which has accelerated the roadmaps for multicore architectures and changed the paradigm from a clock frequency discussion of the past to a new discussion about number of cores and core optimization."


The Tile-Gx36 processor will be sampling in Q4 of 2010, and the other three Tile-Gx processors will roll out in the following two quarters, says Tilera. More information on the Tile-Gx may be found here.

Tilera is sponsoring EE Times' Many-Core virtual conference on Oct. 28, from 11AM to 5PM Eastern time, when Tilera and other companies will discuss "the impending shift to many-core." Registration and more information should be available here.

An eWEEK story on the Tile-Gx should be here.

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