MIPS Technologies is shipping four new 32-bit synthesizable processor cores that support embedded Linux. The new “24K” cores, expected to appear in customer-implemented silicon before 2005, target high-volume applications such as broadband access, wireless, networking, digital television, and office automation.

MIPS first announced the 24K cores in June, 2003, before revealing details in October at the Microprocessor Forum in San Jose.

The four cores include:

• 24Kc core: Base version. Includes a 32×32 Multiply/Divide Unit and configurable memory management unit with TLB or fixed mapping.
• 24Kf core: Includes IEEE 754 hardware floating point support, requiring less than 1.0 sq. mm of additional area in a 0.13 micron process.
• 24Kc Pro and 24Kf Pro core versions: Offer user defined instructions through CorExtend, which is compatible with the industry-standard MIPS32 architecture.

Montavista will work with MIPS to “optimize and tune” its Linux distribution to the 24K cores, according to MIPS.

High performance

MIPS claims the 24K cores are the embedded market's highest performing 32-bit synthesizable processor cores. Intended for 0.13-micron process silicon, the 24K cores will run at 400-550 MHz, producing 1.44 Dhrystone MIPS/MHz, for a total of 576-792 Dhrystones. An eight-stage pipeline works in conjunction with sophisticated hardware branch prediction, MIPS claims, and a full cycle is allocated to the instruction and data cache access to enable performance scalability across a wide range of technologies.

The 24K cores are synthesizable and highly configurable, MIPS claims, enabling designers to tune for performance, area, or power. Designers can specify the primary cache sizes, style of memory management unit, level of debug facilities, and amount of clock gating. The cores also support the Open Core Protocol (OCP) interconnect structure.

OCP

The 24K core interface is standardized on OCP on-chip interconnect technology defined by the Open Core Protocol International Partnership (OCP-IP). MIPS claims this enables designers to build cores that are independent of specific bus protocols and re-usable in subsequent system-on-chip (SoC) designs.

MIPS offers a “SOC-it” system-level controller it says is optimized for OCP, providing a memory controller and bridge to on-chip buses.

Additional chip features include support for MIPS32 Release 2 architecture and the MIPS16e code compression extension.

“High performance in a flexible, synthesizable core is clearly appealing. We also are pleased with the MIPS ecosystem optimizing their product offerings for the 24K core family,” said John Bourgoin, president and CEO of MIPS Technologies.

 
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