Arasan is shipping a suite of synthesizable IP (intellectual property) cores for peripheral interfaces that comply with Mobile Industry Processor Interface (MIPI) standards, for use with ARM or other CPU cores. The cores work with common system buses such as ARM's AMBA AHB bus, and include Linux drivers and stacks, according to the company.

Arason's available MIPI-compliant IP cores include:

• Display Serial Interface (DSI)
• Camera Serial Interface (CSI-2)
• D-PHY IP Core
• SLIMbus IP core (serial low-power inter-chip media bus) implementing a preliminary specification draft

MIPI is an industry group formed by TI, STMicroelectronics (ST), ARM, and Nokia in July of 2003. It aims to cooperatively develop standard, reusable hardware and software interfaces available on a royalty-free basis to MIPI members. Its focus is on mobile phones, but its specs can be applied to other mobile devices, it says.

VP of marketing Kevin Walsh stated, “Arasan Chip Systems has actively contributed to the MIPI organization since 2004. We continue to work with our lead customers to help them deploy these standards into ICs successfully. We are now making this IP and know how available for other MIPI member companies who need to begin to integrate them into their products.”

All of Arason's cores have been validated in silicon, and support either finished or draft MIPI standards, according to the company.

Availability

Arasan's MIPI-compliant IP cores are available to MIPI licensees as source code. “Layer 2 Digital IP” is packaged as synthesizable RTL form, and interfaces with common system buses such as ARM's AMBA AHB bus. “Layer 1 Mixed-signal IP” is foundry dependent, and shipped as GDSII, the company says.

Also included are software drivers and protocol stacks for many associated interface protocols, all targeted for Linux, along with a test environment, synthesis scripts, hardware validation tools, and “complete technical documentation.”

 
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