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Upgraded FPGAs, tools, support Linux

Feb 4, 2009 — by Eric Brown — from the LinuxDevices Archive — 4 views

Altera announced two new FPGAs (field programmable gate arrays), and has upgraded its Linux-compatible FPGA design toolkit. The Quartus II 9.0 toolsuite adds support for the new Stratix IV GT and Arria II GX FPGAs, adds an SSN analyzer tool, and debuts a ModelSim Altera Starter Edition simulation engine.

Rev'd to version 6.0 back in 2006, when Altera added support for 90nm and 60nm-fabricated designs, Quartus II runs on Linux and Windows development hosts. Version 9.0 offers full support for Altera's portfolio of CPLDs (complex programmable logic devices), FPGAs (field-programmable gate arrays) and HardCopy ASICs (application-specific integrated circuits), including the new Stratix IV GT and Arria II GX FPGAs, which are fabbed on 45nm, says Altera.

The high-end Stratix IV GT is the industry's first FPGA family to include integrated transceivers operating at 11.3Gbps, claims Altera. The Stratix architecture is said to be optimized for 40Gbps and 100Gbps interconnects to the host processor. The parts can be used to interface communications gear, high-end test equipment, and military devices with host processors running Linux and other embedded OSes.

The lower-end, low-power Arria II GX devices integrate up to 16 transceivers running at 3.75Gbps, and support protocols such as PCI Express and gigabit Ethernet, says the company. The Arria II GX FPGAs also support targeted protocols including CPRI for LTE and WiMAX equipment, as well as GPON and XAUI.

New features for Quartus II version 9.0 are said to include:

  • SSN Analyzer tool — This new tool offers designer feedback on potential simultaneous switching noise (SSN) violations during pin assignments, thereby speeding board design and improving signal integrity, says Altera.
  • Enhanced SOPC Builder — The SOPC (systems on programmable chip) Builder now offers a “Data Sheet Generator” for easier hand-off between hardware and software engineers, and also adds an enhanced GUI.
  • Metastability analysis — New tools are offered to “auto-recognize” potential metastability circuit issues, and for automating reporting of mean-time-between-failure (MTBF) values, as part of the TimeQuest static timing analysis tool.
  • Pin Planner enhancements — The pin planner is now said to offer a “clock network view” for enhanced management clock resources.

Altera also announced a new ModelSim Altera Starter Edition that replaces its earlier ModelSim Altera Web Edition, and which is bundled free with Quartus II. This lower-end version of the ModelSim Altera Edition is said to offer 50 percent faster simulation speeds, support for all Altera devices, as well as support for Linux and Windows Vista platforms. The extra-cost ModelSim Altera Edition offers 33 percent faster simulation speeds than the Starter Edition, and places no restrictions in design size, says the company.

Stated Chris Balough, senior director of software, embedded, and DSP marketing at Altera, “This latest release of Quartus II software continues our long track record of delivering development tools that consistently reduce design time and increase device performance.”


A beta version of Quartus II 9.0 is available for download now, says Altera. On March 9, the company plans to release the 9.0 production version of Quartus II, as well as the ModelSim Altera Edition (starting at $950 per seat), and the ModelSim Altera Starter Edition. Quartus II subscribers also receive the ModelSim Altera Starter Edition for free, as well as a full license to the IP Base Suite, which includes 11 of Altera's most popular IP (DSP and memory) cores, says the company. The annual Quartus II subscription costs $2,500 for a node-locked PC license.

More information on Quartus II 9.0 may be found here.

More information on the Stratix IV GT FPGA, which is shipping now, should be here.

More on the Arria II GX FPGA, which will ship in May, should be here.

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