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New CMOS technology cuts power use by more than half

Dec 7, 2011 — by LinuxDevices Staff — from the LinuxDevices Archive — 1 views

Fujitsu and SuVolta announced the successful demonstration of a CMOS technology that can cut SRAM (static random access memory) power consumption by more than half. The “PowerShrink” platform will be offered in 65nm products by Fujitsu in 2012, and is available for licensing by others, according to the companies.

SuVolta's PowerShrink was first revealed earlier ths year, as we review later in this story. But this week, SuVolta and initial licensee Fujitsu used the IEEE International Electron Devices Meeting in Washington, D.C., to announce that the technology has been successfully demonstrated — and also to shed a little more light on how it works.

According to the companies, the power consumption of SRAM has steadily ramped downwards as chips get smaller in size. For example, power supply voltages have fallen to around 1.0V for devices produced using 130nm fabrication.

However, power consumption has remained stuck at the 1.0V level even for 28nm devices "because of multiple sources of variation including random dopant fluctuation (RDF)." The latter is described as a "form of device and process variation resulting from fluctuations in the concentration of the implanted dopant or impurity atoms in the transistor channel"; it results in variation in threshold voltage (VT) between different transistors on a chip.

The DDC technology used in PowerShrink
Source: SuVolta via MobileBeat

Fujitsu and SuVolta claim PowerShrink's DDC (deeply depleted channel) technology reduces this variability by establishing regions — pictured above — that allow for different levels of current flow. As a result, a 576Kb SRAM has been shown to work down to 0.425 Volts, the companies announced Dec. 7.

It's said the PowerShrink technology matches well with existing infrastructures including system-on-chip (SoC) design layouts, design schemes such as body bias control, and manufacturing tools. This sets it apart from Intel's Tri-Gate (see later), which also addresses the RDF issue, SuVolta and Fujitsu suggest.

Cross-section of a DDC transistor
Source: SuVolta


SuVolta is a six-year-old company that came out of stealth mode June 6, promising that PowerShrink would reduce power consumption through the new DDC CMOS technology. It promised the platform would also involve DDC-optimized circuits and design techniques, all of which together help drive down voltage by up to 30 percent or more, greatly reducing power consumption.

SuVolta's technology also reduces power leakage by 80 percent or more, maintains a chip's performance, and does not increase production costs, the company claims. Officials said the PowerShrink platform can be used for a variety of IC (integrated circuit) platforms, including chips, SRAMs (static random-access memory) and SoC (system-on-a-chip) architectures.

At the same time, SuVolta's platform can be used with existing fabs, and won't require chip manufacturers to invest in new fabs or equipment. By comparison, Intel has reportedly spent millions of dollars to upgrade its fabs to produce chips with its new 3D Tri-Gate transistor technology, which the chipmaker introduced in May.

The first chips to feature Tri-Gate will be Intel's 22nm, "Ivy Bridge" CPUs, expected to start appearing in April 2012. Specifications have leaked recently for both the desktop versions and lower-power mobile versions, which will reportedly feature "configurable TDP" technology as one route toward power savings.


According to SuVolta and Fujitsu, PowerShrink will be initially available in the second half of 2012, in 65nm Application-Specific Standard Product (ASSP), Application Specific Integrated Circuits (ASIC), and Customer Owned Tooling (COT) products. An overview of the technology can be found on the SuVolta website.

Jonathan Angel can be reached at [email protected] and followed at eWEEK's Jeffrey Burt contributed reporting to this story.

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