Renesas announced a new member of its R-Car series of automotive systems on chip (SoCs). The R-Car H1 has four ARM Cortex-A9 cores clocked at 1GHz, offering up to 11,650 Dhrystone MIPS (DMIPS) performance, plus a Imagination Technologies' SGX-543-MP2 graphics processing unit (GPU) and an optional real-time multimedia engine (MME) based on Renesas' SH4A core.

The R-Car H1 SoC is designed for the high-end car navigation market. With its four 1GHz cores, it's claimed to offer 11,650 Dhrystone MIPS (DMIPS) — or over four times the performance of the earlier dual-core M1 model (see later for background).

The R-Car H1 enables features such as quick-boot, backup camera support, as well as media processing, says the company. It supports operating systems including Linux, Windows Automotive Embedded, and QNX.

R-Car H1 block diagram
(Click to enlarge)

The R-Car H1 SoC is equipped with Imagination's dual-core SGX-543-MP2 GPU, which helps the SoC deliver up to 40 gigaflops per second (Gflops/s) graphics throughput. The GPU supports OpenGL ES 2.0 and OpenVG 1.1 graphics and video technologies, says Renesas.

Video and audio hardware accelerators are also available, helping the SoC achieve 1080p video playback at 60 frames per second (fps), says the company. A Renesas 2D graphics accelerator is also said to be available.

Real-time multimedia engine supports augmented reality

The R-Car H1 SoC is available with an optional dedicated multimedia engine (MME) built around Renesas' IMP-X3 processor. This 800MHz processor is, in turn, based on Renesas' RISC-based SH4A core.

The real-time IMP-X3 image processing unit supports augmented-reality applications, says Renesas. The R-Car H1 is said to make use of the IMP-X3 core to support up to four independent input camera channels, enabling 360-degree camera views and sign recognition, among other applications.

The R-Car H1 SoC offers two independent DDR3 32-bit interfaces "that allow access to different content simultaneously," says Renesas. Peripherals are said to include Ethernet, three USB 2.0 ports with PHY, I2C and serial interfaces, as well as dual CAN channels. Storage and expansion are handled via an SD host interface, a multimedia card interface, PATA and SATA interfaces, and PCI Express expansion, says the company.

Camera and TV tuner interfaces are available, as well as an optional GPS baseband engine, presumably the same CSR SiRF-based package used in the earlier reference platform. In addition, the SoC supports two independent display controllers, and a MOST-150 DTCP audio interface, among other I/O (see spec list below).

Specifications listed by Renesas for the R-Car H1:

Power supply voltage	3.3 V (IO), 1.5 V (DDR3), 1.2 V (Core), 2.5 V (PCIe, MLB), 1.8 V (SDIF UHS-I)
CPU cores	ARM Cortex-A9	SH-4A
Maximum operating frequency	1000 MHz	800 MHz
Processing performance	10000 DMIPS	1760 DMIPS, 5600 MFLOPS
Cache memory	Instruction cache: 32 KB Operand cache: 32 KB	Instruction cache: 32 KB Operand cache: 32 KB
External memory	DDR3-SDRAM (DDR) Maximum operating frequency: 500 MHz Data bus width: 32 bits × 2 channel (4 GB/s × 2 ch)
Expansion bus	Flash ROM and SRAM, Data bus width: 8 or 16 bits
	PCI Express 2.0 (1 lane)
Graphics	PowerVR SGX543MP2 (3D)
	Renesas graphics processor (2D)
Video	Display out × 2 ch (RGB888)
	Video input x 2 ch
	Video decode processor (H.264/AVC, MPEG-4, VC-1)
	Media RAM
	JPEG acceralator
	TS interface
	Video image processing (color conversion, image expansion, reduction, filter processing)
	Distortion compensation module (image renderer) × 4 ch
	Image recognition processor
Audio	Sound processing unit × 2 ch
	Sampling rate converter × 10 ch
	Sound serial interface × 10 ch
	MOST DTCP
Storage interfaces	USB 2.0 host interface × 3 ports (w/ PHY)
	SD host interface × 4 ch
	Multimedia card interface
	Serial ATA interface
In-car network automotive peripherals	Media local bus (MLB) interface × 1 ch (6-pin / 3-pin interface selectable)
	CAN Interface × 2 ch
	IEBus interface
	GPS baseband module
Security	Crypto engine (AES, DES, Hash, RSA)
	Secure RAM
Other peripherals	DMA controller LBSC DMAC: 3 ch / SuperHyway-DMAC: 4 ch / HPB DMAC: 39 ch
	32-bit timer × 9 ch
	PWM timer × 7ch
	I2C bus interface × 4 ch
	Serial communication interface (SCIF) × 8 ch
	Serial peripheral interface (HSPI) × 3 ch
	Ethernet controller (IEEE802.3u, RMII, without PHY)
	Interrupt controller (INTC)
	Clock generator (CPG) with built-in PLL
	On-chip debugger interface
Low power mode	DPS/VS (CPU core, PowerVR SGX543MP2, VPU, IMP) AVS (adaptive voltage scaling) function DDR-SDRAM power supply backup mode
Package	832-pin FCBGA (27 × 27 mm)

Background

A previously announced dual-core Cortex-A9 "M1" version of the R-Car SoC is one of the early support targets for MontaVista Software's new Genivi-compliant MontaVista Automotive Technology Platform (ATP) development platform. ATP is compliant with the open source Linux Genivi In-Vehicle Automotive (IVI) spec.

Renesas used that SoC in a Genivi-compliant IVI reference platform unveiled in June, which incorporates CSR's location and connectivity products, including SiRF GPS chipsets.

That dual-core R-Car SoC offered 2500 MIPS performance at 533MHz, and integrated an Imagination Technologies SGX 530 2D/3D graphics engine. The SoC appears to be based on the R-Car M1 SoC announced in February, which incorporates dual Renesas SH-4A cores. The R-Car M1 can be considered a specialized, automotive-specific cousin of Renesas' dual-core, Cortex-A9-based SH-Mobile APE5R SoC and to a lesser degree, the earlier EMMA Mobile EV0 SoCs.

Availability

Samples of Renesas' R-Car H1 SoC will be be ready in November, equipped in an 832-pin FCBGA (flip-chip ball-grid array) package. Mass production is scheduled to begin in December 2012, and is expected to reach a cumulative 100,000 units per month in December 2013, says Renesas.

More information may be found in this Renesas' R-Car H1 spec sheet, as well as at this separate R-Car H1 product page.

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